Subject: [Fwd: BOUNCE oovhdl@eda.org: Non-member submission from ["Wolfram Putzke"
Wolfram has been trying to post this, but has been bounced due to
Cheers,
PA
-------- Original Message --------
Kamal.Hashmi@icl.com wrote:
> > From: Wolfgang Nebel
I'm not very happy with this interpretation. Of course, both
> SUAVE does have more not strictly OO stuff
Yes and no. We made the experience that it is much easier to explain a
> As I have said before, I regard OO extensions as enhancing the
As far as I understood Wolfgang's remark and questions, this is not
>
> M.M.Kamal Hashmi Design Automation Centre,
> Tel.+44 161 223 1301 x4439 Wenlock Way, West Gorton,
This archive was generated by hypermail 2b28
: Sun Mar 12 2000 - 15:27:39 PST
From: Peter Ashenden (petera@cs.adelaide.edu.au)
Date: Sun Mar 12 2000 - 15:25:24 PST
closing of the email list. I will endeavour to fix the problem asap.
Meanwhile, here is his message...
Date: Sun, 12 Mar 2000 19:04:05 +0100
From: "Wolfram Putzke" <Putzke@Informatik.Uni-Oldenburg.DE>
To: oovhdl@eda.org
Subject: Re: e-mail discussion on review report - VHDLOO
> > Sent: 09 March 2000 13:34
>
> > after those hot discussions in the past, I am very surprised about
the
> > silence on the net after the circulation of Paul's review
>
> I suspect the silence is mostly due to HDL-con which is taking
> place at the moment. At least, I hope it is.
>
> > ...
> > SUAVE targets the system level and abstract data modelling.
> >
> > Objective VHDL targets electronic hardware design and
> > synthesizability.
>
> Hmm. Interesting. I think that your above statements have more
> to do with the interests and intentions of the respective
> proposers rather than the actual content of each proposal.
> I.e. Peter wants to get OO and better abstraction so that
> higher level modelling can be done more easily, whereas you want
> OO so that hardware models can be designed more quickly and
> effectively. (I'm sure Peter and you will correct me if I'm
> wrong on this).
approaches address object orientation, better abstraction, high level
modeling etc.
Further, I think both approaches address primarily improvement of
hardware modeling. (Peter: Correct me if you do not!)
But I think both proposals are developed with not completely
compatible sets of requirements in mind.
Such differences seem to be the domain that is addressed by
the proposals and the weighting of synthesizability. While SUAVE
seems to address also the domain of SLDLs, Objective VHDL
is only intended to be an oo-HDL with the strong requirement
to be synthesizable.
> but its main extensions are in OO data handling. ObjectiveVHDL
> on the other hand has not only OO data but also OO components,
> and the usefulness of the latter is more difficult to explain.
>
hardware designer the usefulness of object-oriented
components compared to the usefulness of object-oriented
extension of the type system. I think the reason for this is that
hardware designers consider components as a very natural candidate
for hardware objects - in object-oriented meaning. For example,
when we asked users what are their wishes for an object-oriented
extensions to VHDL, inheritance of entities was one of the first and
strongest wishes.
However, from language designers point of view the integration of
OO-components in an object-oriented extension of VHDL is not trivial.
> infrastructure of the language - not just the higher levels
> should become easier but every level should also benefit.
>
> However, the problem with OO is mainly with the level of
> training and intelligence required to use it effectively.
> In the software case, I have rarely seen any OO program which
> makes sensible use of inheritance beyond one level. Many
> even fail to make good use of encapsulation and data abstraction.
> Now, in software, one can survive with crap code which doesn't
> work the first time, or on the first few iterations, because
> you can always hack the code. Indeed I suspect that computer
> science courses nowadays teach students to produce a
> nearly-working program as fast as possible, and then pile on
> unstructured fixes afterwards. For hardware and for systems,
> we have to help the engineer in designing a quality system
> which will not only work the first time but also be easy to
> maintain, reuse and refine. So ... do we need to dumb down
> our HDLs from .303s to .22s, or give the kids bazookas ? It's
> the old discussion:
> (capability & flexibility) + (smart engineer) = better products
> (capability & flexibility) + (dumb engineer) = no products
> (capability & flexibility) + (ordinary engineer) = ????
> I seem to be getting off the subject here.
>
> > ....
> > the position
> > and scope the group sees for VHDL in the electronic system
> > design world.
> >
> > - Should it become a system level language?
> > (N.b. if you like ADA style for this, why not use ADA95 for
> > system level?)
> > - Should it support a seamless path to hardware, i.e. should it be
> > synthesizable?
>
> Of course it has to support a path to hardware. Some would
> argue that it already does so - so why do we need OO ? (Use
> 2 sheets of A4 max. - 25 pts).
intended
to be a proclamation that we need object orientation
for hardware synthesis. I understood this as the question whether
the group sees the future of VHDL and its future extensions - if
any - as a system level design language where hardware synthesis
may play only a minor role or whether VHDL should remain mainly
a HDL.
Since our experience has shown that the goals to address the system
level
and synthesizability are very difficult to combine, it seems to be
important for me to find agreement within the group on this
question.
>
> There are people who argue that no HDL can ever be a system
> design language - or should ever try to be one. And sometimes
> I almost believe them - but what do they propose ? UML ? C ?
> C++ ? In my opinion, the biggest single advantage of HDLs is
> that their users expect to create a product that works the
> first time or very nearly so. Most software design cycles
> (especially C-based ones) depend heavily on debugging the final
> product - and this is not acceptable for a system design cycle.
>
> A big problem with VHDL is that any system langauage based on it
> is unacceptable to Verilog users - maybe the merger of OVI and VI
> will come up with an idea.
>
> I have to go now.
>
> - Kamal.
>
------------------------------------------------------------------------
> mailto:Kamal.Hashmi@IEEE.org International Computers Ltd.,
> Fax.+44 161 230 5757 Manchester, M12 5DR, U.K.
--
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