Subject: e-mail discussion on review report
From: Wolfgang Nebel (Nebel@informatik.uni-oldenburg.de)
Date: Thu Mar 09 2000 - 05:34:12 PST
Dear all,
after those hot discussions in the past, I am very surprised about the
silence on the net after the circulation of Paul's review report. In order
to stimulate the discussion a bit, let post my maybe provocative
interpretation of the report:
Both proposals have significant pros and cons.
Both require a lot of clarification in details.
Both meet many aspects of the Greg's requirement doc.
Both need extensions:
- e.g. SUAVE: entity/architecure objects,
- e.g. Objective VHDL: genericity.
SUAVE targets the system level and abstract data modelling.
Objective VHDL targets electronic hardware design and synthesizability.
As stated in our comments on the report, we do not fully agree with all
assessments of Paul, e.g. the difficulty to implement, to prove this you
can download our translator from the web.
In the discussion the group should avoid to get lost in many detailed
technical issues but concentrate on the global picture, i.e. the position
and scope the group sees for VHDL in the electronic system design world.
- Should it become a system level language?
(N.b. if you like ADA style for this, why not use ADA95 for system level?)
- Should it support a seamless path to hardware, i.e. should it be
synthesizable?
As I said: certainly provocative and not unbiased,
looking forward to a vivid discussion,
best regards,
Wolfgang
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