the best way to ensure the future use of VHDL in a world using C, C++ and
discussing SLDL as the system design languages is to position VHDL where it
has its strength and where it is best suited: the hardware domain of
digital electronic systems. Hence I am not scared of C++ or other
languages. They are maybe the better choice for early system (HW + SW)
specification, identification, exploration and partitioning, however, the
power of VHDL is in the more precise specification of timing, concurrency
and its seamless path to low level hardware synthesis.
In order to support these strong points and to take advantage of the
investments made in terms of tools, models, libraries and human skills, we
should enhance VHDL with means which:
- enable a smooth migration from OO system specifications
- enable IP reuse
- enable co-design
Both proposals (SID and OO) address different parts of those goals.
Best regards,
WOlfgang
At 13:07 Uhr -0500 06.07.1999, Bailey, Stephen A (Steve) wrote:
>Kamal states:
>
> "Also we agreed that both groups would kep (sic) an eye on each
> others proposals to make sure that the extensions did not
> come into gross conflict. The full text of the agreement
> is on the SID website (http://www.eda.org/sid) but I have
> appended it to the end of this email anyway."
>
>My point is that having such "side-agreements" is nice and I have
>no problem with the division of responsibility, but it is
>insufficient. The PAR language needs to address the issue
>directly. The side agreements have no weight with the IEEE and
>do not govern the scope/purpose of the proposed standards.
>
>If the intent is compatibility, then what is wrong with codifying it?
>
>Kamal also states:
>
> "On the general problem: Of course, VHDL has to be seen to
> be ONE language and not a set of extensions to a core."
>
>and
>
> "In the longer term, both these (SID and OOVHDL) will
> be consolidated into VHDL but in the short term we should
> let them grow properly before harvesting them.
>
> And the harvester would be the VASG, right ?"
>
>I disagree. VHDL is one language. It is IEEE 1076. VHDL-AMS is
>another language derived from (or built upon) VHDL, it is 1076.1.
>OOVHDL is not VHDL. It will be derived from VHDL. SID is not
>VHDL. It will be derived from VHDL. (Note, I include within language
>derivation the possibility that a new language is nearly 100% backward
>compatible with its parent language. Just as C++ is backward compatible
>with most C code.)
>
>The analogy here is that C++ is not C, but is derived from C. C did not go
>away when C++ became a standard. For the same reasons, VHDL did not go away
>when 1076.1 became a standard and it will not go away if and when OOVHDL and
>SID become standard(s). There is a large user base and a large base of
>existing VHDL models. Many of these users will see no need to use SID or
>OOVHDL for a significant period of time (perhaps forever).
>
>I see no need for the VASG to harvest anything at this point in time. (Of
>course, my opinion is subject to change given reality, but I expect the
>timeframe to be greater than 5 years.) I anticipate that VHDL will grow old
>looking very much the way it does now for the same reason C is growing old
>without becoming C++.
>
>This entire issue is at the heart of the OOVHDL and SID PARs and the scope
>of VHDL 200x. The issue needs to be resolved ASAP.
>
>Kamal also states:
>
> "... this should not be confused with the mechanics of devising
> new extensions. One cannot simply devise and validate
> extensions to a language in large chunks. Smaller extensions
> have to be tried out, often in parallel, and validated
> before they are consolidated into the next version of the
> language. And this is how I regard VHDL "dialects" - those
> extensions of proven worth will get folded into the language."
>
>If SID has not already been validated via ICL's VHDL+ work and OO has not
>already been validated via the Objective VHDL work of Wolfgang Nebel, et al
>and the SUAVE work of Peter Ashenden, et al, then why are we doing the
>prototyping as a standardization activity? This is an inappropriate use of
>the standards forum.
>
>Of course, I'm being rhetorical here because (I think) both the SID and
>OOVHDL groups would insist that the prototype work has been done and the
>concepts proven. Therefore, both are at an appropriate stage for
>standardization.
>
>My points remain:
>
>1. VHDL is a mature language with a large user base.
>2. Therefore, VHDL cannot change significantly without significant negative
>impact to that user base.
>3. Both OOVHDL and SID are essentially defining the next generation
>(successor to) VHDL (not the next version of VHDL).
>4. To increase the chances of success for the next generation VHDL, the two
>groups should merge their standardization and language design activities to
>generate one language.
>5. Failure to do so will risk the fragmentation of an emerging market into
>segments too small to support tool and infrastructure development. (IMHO,
>it guarantees that the market will be so fragmented.)
>6. Failure to resolve this issue ASAP risks being fatally late to market
>with a solution/product. Witness all the non-VHDL derivatives at this
>year's DAC (C++, Java, Verilog/C -- also known as Superlog). These are the
>competitors, not 1076! Can we afford to wait another 2-5 years for separate
>standardization of OOVHDL and SID and then another 5 years after that for
>the two to be merged? By then, VHDL will be an old language with a
>shrinking user base and OOVHDL and SID will have been relegated to history's
>ash heap. Of course, merging the two activities does not guarantee success
>of VHDL TNG (VHDL The Next Generation), but failing to merge does guarantee
>failure (IMHO).
>
>-Stephen Bailey
>Chair, IEEE 1076, 1076a
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