I have been quiet so far in this discussion because we had this discussion
2 years ago. After that Steve Bailey proposed to go for a trial use
standard for the OO extensions which would give the community the
opportunity to test these extensions on the one hand very early but on the
other hand independently from other extensions. The agreement between both
groups should help to avoid conflicting concepts in both parts (SID and
OO). Hence I fully support Kamal in going for a trial in both cases,
however, with the goal to consolidate whatever will be the outcome after
user experience into one common VHDL.
Considering the complexity of current VHDL and the small subsets typically
used, I think our procedural proposal will be much more efficient and fast
than a consolidation effort upfront which will most likely result in a more
academic and overloaded language than the consolidation of proven smaller
language extensions.
Going further, once we know which communication concepts and which OO
concepts are really most benefitial for the VHDL users we could start to
prune the language from unused parts of current VHDL and hence come up with
really purified VHDL in contrast to just another - even consolidated -
extension.
Regards,
Wolfgang
At 17:41 Uhr +0100 06.07.1999, Kamal.Hashmi@icl.com wrote:
>Right.
>There certainly is some interesting discussion going on here.
>
>A) I'll start with Jean Mermet's and John Hillawi's concerns
>regarding SUAVE and SID: Given the range of the SUAVE and
>SID extensions this is certainly a reasonable concern in
>the area of communications abstraction.
>
>Jim Heaton, myself and Peter Ashenden also shared this
>concern, and at the meeting last year between the two
>groups (at FDL'98) we agreed that the OO group would
>not consider the SUAVE communications extensions but that
>Peter would join the SID group and address his ideas
>in this sphere to this group.
>
>Also we agreed that both groups would kep an eye on each
>others proposals to make sure that the extensions did not
>come into gross conflict. The full text of the agreement
>is on the SID website (http://www.eda.org/sid) but I have
>appended it to the end of this email anyway.
>
>
>B) Now onto Steve Bailey's and Ron Waxman's concern about
>the danger of splitting VHDL into many dialects.
>This is, of course, not a problem specific to the SID and OO
>groups - though it may be more easily noticed with these
>groups since they are both perceived as addressing the
>same "System" area (although OO is useful in far more).
>
>On the general problem: Of course, VHDL has to be seen to
>be ONE language and not a set of extensions to a core. But
>this should not be confused with the mechanics of devising
>new extensions. One cannot simply devise and validate
>extensions to a language in large chunks. Smaller extensions
>have to be tried out, often in parallel, and validated
>before they are consolidated into the next version of the
>language. And this is how I regard VHDL "dialects" - those
>extensions of proven worth will get folded into the language.
>
>On the specific SID-OO problem: Both these groups have a
>significant amount of capability to add to VHDL in their
>extensions. Each needs to be tried and tested before it
>gets merged into the main language. If we put these
>together in the early stages then we run the risk of
>sinking the boat. In the longer term, both these will
>be consolidated into VHDL but in the short term we should
>let them grow properly before harvesting them.
>
>And the harvester would be the VASG, right ?
>
>Just my personal tuppence,
> Kamal.
>------------------------------------------------------------------------
> M.M.Kamal Hashmi Design Automation Centre,
> mailto:kamal.hashmi@ieee.org International Computers Ltd.,
> Tel.+44 161 223 1301 x4439 Wenlock Way, West Gorton,
> Fax.+44 161 230 5757 Manchester, M12 5DR, U.K.
>------------------------------------------------------------------------
>
>============================================================
>SID - OO study groups agreement (reached at FDL'98):
>----------------------------------------------------
>There are 2 study groups active currently in complementary
>domains:
>
>1. System level Interface Design extensions to VHDL, (SID),
>with the scope of Interfaces and Communication across
>Interfaces.
>2. Object Oriented extensions to VHDL (OO VHDL) with the
>scope of language techniques for OO modelling.
>
>There are 3 paths of development in work at this time:
> 1. VHDL+ in the SID Study Group.
> 2. OO VHDL
> 3. SUAVE both in the OO group.
>
>
>The areas of coverage for the paths are
> SID-------- VHDL+
> INTERFACES AND COMMUNICATION THROUGH / ACROSS INTERFACES.
> OO--------OO VHDL
> LANGUAGE TECHNIOUES FOR OO MODELLING.
> SUAVE-----OO VHDL
> COMMUNICATION AND LANGUAGE TECHNIOUES FOR OO MODELLING.
>
>
>It has been agreed that the SID & OO Groups will follow
>the paths as defined above. Developments of SUAVE will be
>addressed to the SID/OO Group as appropriate.
>
>There will be joint membership of both groups and complete
>transparancy of working papers and proposals to ensure
>that overlap and conflict are eliminated.
>
>SID and OO Groups intend to proceed independantly in time
>to produce drafts for ballot.
>============================================================
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