As VHDL has matured and reached a level of stability, we must ensure that
follow-ons (enhancements) are under tight technical control. The structure
of the DASC must be reviewed to see how such controls can be established
and enforced. We do not want to lose the gains we have worked hard to
achieve.
Ron Waxman
At 03:00 PM 7/5/99 -0600, Stephen A. Bailey wrote:
>No where, in either the purpose or the scope, does the PAR provide direction
>to be compatible with the work of the SID group. Once again, I reiterate my
>point that there should be a single successor to VHDL 1076 as we know it
>today. Neither the SID nor the OOVHDL PARs address the compatibility
>issue. I cannot support either PAR until this issue is addressed. I would
>prefer to see the two groups merged into one (two technical committees can
>continue to work the different areas, but the result is one 1076 follow-on
and
>not two dialects). However, at minimum, the PARs need to address the issue.
>
>Victor, this issue needs to be discussed at the next DASC steering
>committee meeting. When and where is it?
>
>-Stephen Bailey
>Chair, IEEE 1076, 1076a Working Groups
>
>> At the 25 June meeting of the OOVHDL Study Group, the following revised
>> text for the draft PAR was agreed upon. The text is open for comment
>> until 2 July. After that time, I will hold an email vote closing 30
>> July.
>>
>> Please direct comments to the list (oovhdl@eda.org).
>>
>> Thanks.
>>
>> Cheers,
>>
>> PA
>> --
>> Dr. Peter J. Ashenden Email: petera@cs.adelaide.edu.au
>> Dept. Computer Science peter.ashenden@acm.org
>> University of Adelaide peter.ashenden@computer.org
>> Adelaide, SA 5005 Phone: +61 8 8303 4477
>> Australia Fax: +61 8 8303 4366
>>
>> WWW: http://www.cs.adelaide.edu.au/~petera (includes PGP public key)
>>
>> -------------------------------------------------------------------------
>>
>> Purpose
>>
>> Object-oriented and generic modeling offer mechanisms for abstraction
>> and encapsulation of descriptions of designs and testbenches, and thus
>> provide significant potential for reuse. VHDL currently lacks many
>> features for these styles of modeling, which are important for
>> managing the increasing complexity of design descriptions. The overall
>> goal is to increase the productivity of electronic system design
>> engineers.
>>
>> Scope
>>
>> To define new language features and to extend existing language
>> features of VHDL to allow object-oriented and generic modeling of
>> electronic systems. Among the approaches to be considerd are:
>> expression of abstract data types, including encapsulated data and
>> applicable operations; inheritance of data and operations;
>> polymorphism of objects; and genericity of types.
>
>
>
>
-------------------------------------------------------------------->>>>
Ronald Waxman r.waxman@computer.org
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