OO-VHDL Study Group Meeting at DAC'99 - Minutes

by Wolfgang Nebel

DC Dave Clemens,                OrCAD

WP William Paulsen              Cadence                         (part time)

PM Paul Menchini                OrCAD

DB Dave Barton                  Intermetix                      (part time)

JM Jean Mermet                  ECSI                            (part time)

GP Greg Peterson                FTL

PF Peter Flake                  Co-Design Automation Inc.

PA Peter Ashenden               Univ. Adelaide

AB Alessandro Balboni           Italtel

WE Wolfgang Ecker               Infineon Technology

WN Wolfgang Nebel               OFFIS

JH Jim Heaton                   ICL                             (part time)

KH Kamal Hashmi                 ICL                             (part time)

BK Bob Klenke                   VCU                             (part time)

AZ Alex Zamfirescu              ASC                             (part time)

RP Roberto Passerone            UC Berkeley                     (part time)

JH John Hillawi                 DA Solutions                    (part time)

1. Welcome

2. Industrial Design Experience Using Objective VHDL (A. Balboni)

3. OO-VHDL Requirements Doc.

4. Proposed PAR

5. Report on Comparison of SUAVE and Objective VHDL proposals

6. Process of Review of SUAVE and Objective VHDL Proposals

7. A.O.B.

PA opened the meeting. The agenda has been ammended by item 2.

AB presented briefly Italtel, which is a 50% subsidary of Siemens and is designing telecom equipment. Italtel used Objective VHDL at the entity and the type class level. AB gave a brief intro into Objective VHDL. The work has been done within the EUROPEAN REQUEST project. Within the project a set of object libraries has been developped, including, e.g. several kinds of filters. AB explained the design flow used built on the Leda Objective-VHDL2VHDL translator and a standard VHDL based back end design flow. One example was a stack described in 218 lines of Objective VHDL. The translated VHDL code had 275 lines of code. AB emphasized the transparency of the translation. The translator does not change the level of abstraction. The OO methodology adopted allows to create more compact and well structured code. The output of the translator meets well the description style accepted by the Behavioral Compiler. The synthesized hardware corresponds well to the Objective VHDL input specification. AB stated that Italtel noticed the way Objective VHDL motivates the designer to structure his descriptions enables modelling which is better suited for behavioral synthesis, because he is more interested to concentrated on functionality.

Conclusion:

- Allows design reuse

        decrease design time through specialization hierarchy and testing time

        increasing reliability

- Expressivity

        increase abstraction (coupled with behavioral synthesis)

- further needs

        optimization of the VHDL translator

        definition of message passing templates

        definition of a library of basic objects

        analyse the relationships with behavioral compilers

Questions:

KH: Size of designs? AB: Small blocks in the project so far.

KH: How did real designers comment? AB: Young designers more enthusiastic than older ones.

PA presented the history of the requirement collection process. In particular the requirements collected from the REQUEST project and having been voted as a starting point for the requirements of the OO-VHDL Study Group.

GP is now chairing the requirements collection group of the OO-VHDL Study Group and presents the sub-commities requirements report. GP distributed his report. Starting point was the original 1983 requirements document for VHDL. Overall objective is to improve productivity. Scope: no consideration of gate-level. GP did not make destinction between SID and OO Group. Economic considerations are important, e.g. compatibility with existing models. Benefits should be abstract modelling, architectural exploration, ...

PG has clustered the requirements: (underlined caused discussion)

GP to add a paragraph of explanatory text to each of the listed requirements in the document, and to make the amended document available on the web site.  PA to call for votes on partial ordering of the requirements.

After some discussion and refinement the following text was agreed to be distributed by PA by e-mail before July 2nd. Then one week of comments (until July 9th) should be followed by an electronic voting until July 30th.

WN presented the results of the comparison activity done by PA and Martin Radetzki in Adelaide late 1998. This was a follow up action of the Study Group Meeting in Santa Clara.

The objective was to compare SUAVE and Objective VHDL w.r.t. similarities and differences as well as to investigate the possibility to merge both proposals. The results of the meeting have been documented in a report, which is downloadable from the OO-Groups page.

Similarities of both approaches include:

- idea of type for class

- inheritance

- abstract classes and methods

- instantiation of classes

- local classes

- class wide types for polymorphism

- dynamic dispatch of methods (for class wide types)

Reconcilable differences which, however, could be unified include:

- aggregates of class-typed values which are not supported by Objective VHDL

- visibility modes of class attributes

- abstract methods (difference in explicity)

- initialization

- predefined operators

- parameter passing mechanism (SUAVE: by reference; Objective VHDL: as VHDL)

- infix operators only in SUAVE

- type converison

- invocation of overridden methods

Fundamental differences:

- choice of class construct

        In SUAVE type classes are declared separate from the methods while

        in Objective VHDL types and methods are combined into classes

- use of class wide types

        In SUAVE a reference mechanism is used while

        in Objective VHDL a value semantics is applied.

        Discussion: PA stated that SUAVE could be ammended by a value semantics.

Other aspects include the genericity which is limited to constant generics in Objective VHDL while type/subprogram/package generics are allowed in SUAVE. The comparison did not include a discussion of entity/architecture types, active objects, and communication because these issues have been thought to be outside the scope of the group. Given the requirements proposal by GP, however, some of these issues might have to be taken up again.

In conclusion, PA and Martin Radetzki decided that a merger of both proposals is not feasible, because even given a proposal by WN to consolidate the class definition mechanism works, the impact on both language proposals would be unrealisticly high.

PF asks about the relation between OO proposals and SID. PA explains that OO data modeling and type genericity are in the domain of OO while abstract communication is in the domain of the SID group. However, both activities are not decoupled.

The proposal has been accepted unanimously by vote of the group.

AB suggests to include a person with Verilog experience on the panel because some parallel activity is ongoing in the Verilog community Janick Bergeron was proposed. WN suggest to include an industrial user.

Panel nominations are so far:

Paul Menchini           confirmed

John Willis             confirmed

Dough Dunlop            subject to confirmation

Dave Barton             subject to confirmation

Jacques Rouillard       confirmed

Alain Fonkoua           confirmed

Wolfgang Ecker          confirmed

Janick Bergeron         subject to confirmation

Next meeting Sept. 2nd., 1999, 9:00-13:00, at FDL, Lyon, France

http://www.ecsi/org/ecsi/fdl

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________________________________________________________________________
 Prof. Dr.-Ing. Wolfgang Nebel           Tel.:      +49-(0)441-798-4519
 Carl v. Ossietzky University            Secretary: +49-(0)441-798-4517
 D-26111 Oldenburg                       Fax:       +49-(0)441-798-2145
 Germany                                 Home:      +49-(0)441-   52826
                                         Mobile:    +49-(0)171-62 52827
                                 e-mail:             nebel@computer.org
                                 or:  nebel@informatik.uni-oldenburg.de
                                 http://eis.informatik.uni-oldenburg.de
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