RE: Proposed PAR for trial use standard

Bailey, Stephen A (sbailey@veribest.com)
Thu, 27 May 1999 15:33:36 -0500

I am personally still struggling to understand the benefits of doing the SID
work separate from the OOVHDL work. And, if I extend it just a bit further,
we could include the system-level enhancement activities for VHDL 200x. The
most concrete thoughts I have seen on system-level enhancements pertain to
higher level inter-process communication mechanisms which is central to SID
and implicit in method invocation (messages).

My motivation is to try to maximize the resources we have while also
developing something that users will find very valuable and compelling.

Therefore, I'd like to recommend that we once again explore the possibility
of combining the 3 separate efforts in an attempt to significantly move VHDL
forward. I am not making this recommendation so that VASG can control it.
I frankly think it would be better to keep it as a separate group, but only
one group and not 3.

-Steve Bailey
Chair, IEEE VASG

-----Original Message-----
From: Peter J. Ashenden [mailto:petera@cs.adelaide.edu.au]
Sent: Wednesday, May 26, 1999 10:02 PM
To: oovhdl@eda.org
Subject: Proposed PAR for trial use standard

Dear colleagues,

This message presents a draft of the Scope and Purpose of a PAR to
develop object-oriented extensions to VHDL. First, here is some
background.

Some time ago, the OOVHDL Study Group agreed to work towards a PAR for a
Trial Use standard. Since then group has considered two proposed
language extensions: SUAVE, proposed by Peter Ashenden from the
University of Adelaide and Phil Wilsey from the University of
Cincinnati; and Objective VHDL, proposed by Wolfgang Nebel and
colleagues from the University of Oldenburg. Both proposals provide
language mechanisms for object-oriented and generic modeling of data.

SUAVE additionally provides communication mechanisms for high-level
models. In a meeting at Lausanne last year, it was agreed that the
high-level communication aspects of SUAVE would be considered by the SID
Study Group, and be out-of-scope for the OOVHDL Study Group.

Objective VHDL additionally provides mechanisms for object-oriented
design entities (extensible entities and architectures). However,
Wolfgang suggests that these mechanisms be considered as a separate
development, and that the OOVHDL Study Group focus on OO data modeling.

Given this background, Wolfgang and I now proposed the following draft
Scope and Purpose for the PAR:

Scope

To define new language features and to extend existing language
features of VHDL to allow object-oriented and generic modeling of data
in VHDL models. The features will provide for: expression of abstract
data types, including encapsulated data and applicable operations;
inheritance of data and operations; polymorphism of objects; and
genericity of types.

Purpose

Object-oriented and generic modeling offer better mechanisms for
abstraction and encapsulation of descriptions of designs and
testbenches, and thus provide enhanced potential for reuse. VHDL
currently lacks features for these styles of modeling, which are
important for managing the increasing complexity of design
descriptions.

I invite your comments by email to this mailing list over the next few
weeks, so that we can vote informally at the DAC meeting. A formal vote
will subsequently be held my email.

Cheers,

PA
(Co-chair)

-- 
Peter J. Ashenden                  Email: petera@cs.adelaide.edu.au
Dept. Computer Science                    peter.ashenden@acm.org
University of Adelaide                    peter.ashenden@computer.org
Adelaide, SA 5005                  Phone: +61 8 8303 4477
Australia                          Fax:   +61 8 8303 4366


WWW: http://www.cs.adelaide.edu.au/~petera  (includes PGP public key)