Re: Proposed PAR for trial use standard

M.M.Kamal Hashmi (kamal@wg.icl.co.uk)
Thu, 27 May 1999 11:17:55 +0100 (BST)

G'day Folks,

What a fortnght of sport so far - the World Cup, and United win
the Treble while sleep-playing !

I have a few comments on the PAR ...
Firstly, shouldn't the Purpose come before the Scope ?

> Scope
>
> To define new language features and to extend existing language
> features of VHDL to allow object-oriented and generic modeling of data
> in VHDL models. The features will provide for: expression of abstract
> data types, including encapsulated data and applicable operations;
> inheritance of data and operations; polymorphism of objects; and
> genericity of types.

Good Scope - succinct and to the point. Good idea to list out exactly
what will be featured - saves argument later.

> Purpose
>
> Object-oriented and generic modeling offer better mechanisms for
> abstraction and encapsulation of descriptions of designs and
> testbenches, and thus provide enhanced potential for reuse. VHDL
> currently lacks features for these styles of modeling, which are
> important for managing the increasing complexity of design
> descriptions.

The Purpose is still general OO - it would do for the next stage of
OO with the Objective VHDL extensions. Surely it should tie in with the
new Scope ? And, of course, OO helps design as well as reuse.

I suggest:
Object-oriented and generic modeling provides useful mechanisms for
the abstraction and encapsulation of data in designs and
testbenches, and thus provide enhanced capability for their design
and reuse.
VHDL currently lacks features specific to these styles of modeling
which are important for managing the increasing complexity of design
descriptions.

- Kamal.