OO-VHDL study group

Introduction

The study group on object-oriented extensions to VHDL was established in late 1993 in response to growing interest in the idea of applying object-oriented techniques in hardware design. Similar as in software domain the object-oriented modeling paradigm can be considered as a promising way to manage the ever increasing complexity of hardware models and raise the productivity significantly.

Group Objectives

The study group was established to build an understanding of what "object-oriented VHDL" might mean, define and discuss requirements for object-oriented VHDL, examine the expected benefits which result from an application of the oo-paradigm, and define and discuss proposals for object-oriented extensions to VHDL.

Activities and Achievements:

03/19/98 study group meeting at Spring VIUF`98, Santa Clara (minutes)

05/06/98 study group has elected Peter Ashenden and Wolfgang Nebel as Co-chairs

06/19/98 study group meeting at DAC`98, San Francisco (minutes)

09/12/98 study group meeting at FDL`98, Lausanne (agenda, minutes)

03/09/99 study group meeting at DATE'99, Munich, Germany (tentative agenda)

06/25/99 study group meeting at DAC , New Orleans, US (minutes)

08/02/99 study group meeting at FDL99, Lyon (minutes)

03/07/00 study group meeting Mentor Graphics, San Jose (minutes)

Review procedure and schedule for SUAVE & Objective VHDL proposals

03/27/00 study group meeting at DATE 2000, Paris (minutes)

06/09/00 study group meeting at DAC2000, Los Angeles (agenda,minutes)

Planned next meetings:

09/05/2000 study group meeting at FDL 2000, Tuebingen, Germany 4 pm. - 6 pm., venue to be advised.

Tools

download the free demo version of the Objective VHDL to VHDL precompiler

Links and further information:

Contacts:

Peter Ashenden (petera@cs.adelaide.edu.au)
Wolfgang Nebel (nebel@informatik.uni-oldenburg.de)

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