VHDL MATH PACKAGE WORKING GROUP, P1076.2 Minutes of meeting in Grenoble, 23 September 1994 Present: Jose Torres, Synopsys (Chair), jose@synopsys.com Peter Sinander, European Space Agency (Minutes), psi@wd.estec.esa.nl Sylvie Hurat, Thomson-CSF, hurat@sctf.thomson.fr Adam Morawiec, Artemis/ECSI, Adam.Morawiec@imag.fr Next meeting: most probably at VIUF in November at Washington, DC, USA. 1. INTRODUCTION P1076.2 Working Group members are: - J. Torres, Synopsys (Chair) - C. Swart, Mentor Graphics - A. Zamfirescu, Intergraph - D. Hanson, University of Mississippi The VHDL math packages consist of basic functions and type conversions for real and complex types, and will be placed in the IEEE library. There are two packages: MATH_REAL and MATH_COMPLEX. A testbench will be prepared for each package, but it will not formally be part of the standard just a reference (see further section 4). 2. NEW RELEASE OF MATH PACKAGE A new release of the math package will be placed on the VI server in October. Several bugs were detected in the previous version, which have been corrected in the new version. The package is available through anonymous ftp from vhdl.org, in the directory /vi/math/package, file names are: math_head.9.30.94.vhd math_body.9.30.94.vhd The packages can be retrieved as follows: ftp vhdl.org username: anonymous password: ftp> cd /vi/math/package ftp> get math_head.9.30.94.vhd ftp> get math_body.9.30.94.vhd ftp> bye 3. PLANNED ACTIVITIES The work on the testbench is still in progress. There is a need for more effort in this task, and anybody that could provide help should contact Jose Torres. The ballot constituency will take place in October/November, by invitation through the math package reflector as well as direct e-mail to certain persons. The balloting is planned for January 1995. The IEEE approval is currently foreseen for mid 1995. There is a possibility that Rita Clover will help with the preparation of the standard, which need to be written according to the IEEE standard format. 4. IMPLEMENTATION DETAILS The body of the math package is written in VHDL, though in most cases simulator vendors will implement it in C-code for optimized performance. The minimum precision is that of the VHDL LRM; minimum 6 bits precision in a range from -1E38 to 1E38 is required, but an implementation is allowed to provide higher precision. Sylvie Hurat stressed the importance of a double precision version of the Math packages becoming available, since this is required for system simulations and analog VHDL. It is important that other WGs (particularly the analog WG) do not define their own packages. It is proposed to ballot the single-precision version of the packages now, and later create a double precision version by overloading the funtions when the double precision data type is defined by the analog WG. No new functions should be added for the double precision versions. See further section 5. It was agreed at the meeting that the precision of the constants declared should at least cover the IEEE-754 double precision accuracy, i.e. 16 digits. It is required that the functions detect and report invalid parameters (out of range), but underflow/overflow detection is optional. The severity level can be defined by the user, with the default being Error. The package will be written to conform with both VHDL-1987 and VHDL-1993. 4. TESTBENCHES AND VERIFICATION APPROACH The testbench, which is not part of the standard and will be provided as a reference only. In principle, the test bench will exercise all data points for all the functions in each package, it will compare the outputs from an implementation against a set of "golden" outputs, and will produce a report with differences found. Final details on the process are still being worked out. It is important to note that the math package results may be slightly different on different workstation combinations due to the workstations particular support for floating point arithmetic, which may not be immediately apparent to the average VHDL user. However, since most workstations use the IEEE-754 floating point format the variations will be limited in practice. 5. OPEN ISSUES Jose Torres has proposed to start the balloting process even though the testbenches have not been completed. This was considered as a practical approach by the meeting participants, since the testbench is not part of the standard. The final decision will be taken by the WG members. It is desirable that all IEEE packages should report errors in a standardized way, so contact is necessary with the other IEEE WGs. The contents of the error messages should also be reviewed to be understandable and useful for the average VHDL user (and not only for numerical experts). The coordination with the analog WG is minimal, no formal feedback has yet been received from this WG. However, Sylvie Hurat who is following that WG stated that they have basically defined what functions they need. Another question is whether double precision reals will be called Real or renamed to a new type called Float. Jose Torres will contact J.-M. Berge or A. Vachoux to obtain formal comments from the analog WG. 6. MISCELLANEOUS Jose Torres mentioned that the activity on the e-mail reflector has been low during the past months, but should increase with the event of the new release of the package and the balloting process. It was stated that no problems are expected with vendors adopting the Math packages, since this topic does not seem to be a controversial one and different vendors have provided input or offered a version of their own packages as a starting point for this standard.