Re: Adding E-flavor to PSL

Hi Srinivasan,

The latest P1850 has just been submitted to RevCom for final approval. Hence, IEEE Std 1850-2010 will be released this spring. I currently don't see another PAR starting up for some time, and 3 to 5 years out before another LRM would be released.

When a new PAR does start up, I suggest that you get involved in the standard and propose the extension that you are suggesting.

Best regards,

-Harry

On Mar 3, 2010, at 9:50 AM, Srinivasan Venkataramanan wrote:

> Hello,
>
> Please fwd to relevant 1850 mailing list as I couldn't figure out how to add myself to that list (is it majordomo based?)
>
> Has anyone requested for a E-flavor of PSL? I know both these languages are under little less pace in growth, but potentially this is an interesting value proposition, especially considering recent DVCon 2010 presentations on revival of Specman/E language. In a paper entitled “Apples to Apples HVL comparion” the CDN authors wrote the following. I had a chat with Ajeetha here and we believe a e-flavored PSL will be a better fit here.
>
>
> Any comments? If you like it, how do we take this forward?
>
> Thanks
>
> Srini
>
> www.cvcblr.com
>
>
>
>
>
> Extract from DVCon paper
>
>
> ---
>
> 3.5 Design Related Assertions
>
> Both e and SystemVerilog support assertions. However,
>
> SystemVerilog assertions (SVA) have some advantages over
>
> those created in e. One strong advantage is the ability to use
>
> SVA’s in multiple verification flows. SVA’s can be used in
>
> formal analysis, they can be used in the traditional simulation
>
> flow, and they can be synthesized for use in hardware
>
> acceleration environments. Another reason SVA’s have some
>
> advantage over e assertions is the idea of maintaining assertions
>
> within the design by the designers. This is a great area to share
>
> some of the verification work with the design team without
>
> forcing them to learn a completely new language or new
>
> programming paradigms like AOP or OOP. Designers can help
>
> by creating both checking and coverage related assertions,
>
> which inherently reflect the design intent, as they are creating
>
> the design.
>
> It is important to remember that SVAs also work very
>
> nicely in conjunction with an e testbench environment. Sort of
>
> the best of both world type scenario. In fact, there are a number
>
> of hooks added into Specman to allow SVAs to “call back” into
>
> the e testbench for additional processing.
>
> ---
>

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