RE: Verification unit bindings -- text change proposal

Johan,

This approach relies upon support for hierarchical pathnames that refer to items in other modules ("out of module references", or OOMRs). Although OOMRs are allowed in Verilog, they are not allowed in VHDL - so how do you expect this to work in a VHDL context? Do you mean to extend VHDL expressions used in the Boolean layer of a PSL directive to allow such references? If so, how will you specify that, and where?

Regards,

Erich

| -----Original Message-----
| From: owner-ieee-1850-extensions@eda.org
| [mailto:owner-ieee-1850-extensions@eda.org] On Behalf Of
| Johan Alfredsson
| Sent: Monday, January 24, 2005 10:16 AM
| To: ieee-1850-extensions@eda.org
| Subject: Verification unit bindings -- text change proposal
|
|
| Hi all,
|
| The following is a proposal how the LRM text ought to be
| changed/clarified concerning the semantics of verification
| unit bindings, specifically to take care of the ambiguity
| that 7.2.1 talks about duplicating the contents of a
| verification unit while the second exampel (on p. 92) implies
| that not only the contents but also the verification unit
| itself is duplicated.
|
| Johan Alfredsson
| Jasper Design Automation
| www.jasper-da.com
|
| --------------------------------------------------------------
| ----------------
|
| Change proposal for 7.2.1
|
| p. 91
|
| Insert "Note that the verification unit itself is not
| duplicated." after "If the verification unit is explicitly
| bound to a module, then this is
| equivalent to duplicating the contents of the verification unit and
| binding each duplication to one instance."
|
|
| p. 92
|
| Change the second example (lines 4-20)into
|
| "As a second example consider
|
| vunit ex2a(mod1) {
| assert never (ena && enb);
| }
|
|
| The verification unit is bound to mod1. If this module is
| instantiated
| twice in the design, once as top_block.i1.i2 and once as
| top_block.i1.i3,
| then vunit ex2a is equivalent to the following vunit:
|
| vunit ex2b(top_block.i1) {
| assert never (i2.ena && i2.enb);
| assert never (i3.ena && i3.enb);
| }"
|
| --------------------------------------------------------------
| -----------------
|
|
Received on Mon Jan 24 09:41:50 2005