RE: gdl flavor of HDL_VARIABLE_TYPE

Tej,

Cindy has provided a nonterminal for the GDL flavor of your proposed HDL_VARIABLE_TYPE flavor macro - see below. Please add this to the next version of your data type extensions proposal.

By the way, the convention for flavor macros so far has been to refer to a single nonterminal in each case, rather than to multiple alternative nonterminals, as your proposal does for Verilog:

| > / Verilog : task_port_type | reg [signed] [range]

We adopted that convention to avoid intermingling the concept of 'flavor macro' (which requires a consistent selection as a function of underlying language) with the concept of 'production' (which allows selection of a different alternative in each case). When there was no existing single nonterminal to use in a flavor macro, we defined a nonterminal in the PSL grammar to serve instead, e.g.,

Flavor Macro HDL_DECL =
    SystemVerilog: /SystemVerilog/_module_or_generate_item_declaration
  / Verilog: Extended_Verilog_Declaration
  / VHDL: /VHDL/_block_declarative_item
  / GDL: /GDL/_module_item_declaration

Extended_Verilog_Declaration ::=
    /Verilog/_module_or_generate_item_declaration
  / Extended_Verilog_Type_Declaration

Extended_Verilog_Type_Declaration ::=
    integer Integer_Range list_of_variable_identifiers ;
  | struct { Declaration_List } list_of_variable_identifiers ;

where Extended_Verilog_Declaration was defined in the PSL grammar to avoid listing multiple alternatives for Verilog in the HDL_DECL flavor macro. You may want to do something similar in your proposal.

Regards,

Erich

| -----Original Message-----
| From: Cindy Eisner [mailto:EISNER@il.ibm.com]
| Sent: Sunday, January 09, 2005 2:59 AM
| To: Erich Marschner
| Subject: gdl flavor of HDL_VARIABLE_TYPE
|
|
|
|
|
| erich,
|
| at the last extensions meeting, you asked me to supply a gdl
| placeholder for the flavor macro HDL_VARIABLE_TYPE. here it is:
|
| >Flavor Macro HDL_VARIABLE_TYPE =
| > System Verilog : data_type
| > / Verilog : task_port_type | reg [signed] [range]
| > / VHDL : subtype_indication
| > / GDL : gdl_variable_type
|
| cindy.
|
| --------------------------------------------------------------------
| Cindy Eisner
| Formal Methods Group
| IBM Haifa Research Laboratory
| Haifa 31905, Israel
| Tel: +972-4-8296-266
| Fax: +972-4-8296-114
| e-mail: eisner@il.ibm.com
|
|
|
Received on Sun Jan 9 07:20:30 2005