Extensions SC status - 23 Nov 2004

Extensions Subcommittee Status - 23 Nov 2004

For discussion in the Extensions subcommittee meeting today.

LRM Change Proposals:
===================

Group A (Erich)
  - drafted changes to define determination/inheritance of clock context
  - identified related issues in 4.4.1 (clocked and unclocked eval) and 5.2.3.* (defn of rose/fell/etc.)
  - still need to draft changes for optional clock parameter

Group B (?)

Group F (Erich)

Group I (?)

Issues Discussed and Resolved:
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[5.0] Group A (7,40) - clock context for rose/fell/prev/stable and endpoints
[5.0] Group B (9,10,11,12) - initial values of prev, rose, fell, and clarification of prev(a(i)), prev(f(i))
[4.7] Group F (15,17,27) - VHDL flavor return types of built-in functions, and interpretation of 'H', 'L'
[2.0] Group I (36) - clarification of 'replication' with forall

Issues Remaining to be Resolved:
==========================

[3.0] Group I (25,41) - extension of forall to directives, and to sub-properties
[4.0] Group E (13) - additional simple subset restriction

[5.0] Group D (8,38) - extension of parameter classes to include Bit, BitVector, Numeric, String
[4.0] Group H (21) - portable flavor of PSL
[4.0] Group J (31) - improved non-determinism
[3.7] Group C (5,19,23,26,30,33) - vunit binding, scoping, inheritance, and parameterization
[3.0] Group G (20) - abort refinement
[?.?] Group K (42,43) - cover extensions for data-oriented, transaction-oriented coverage
[?.?] Group L (44) - SystemC flavor of PSL

Issues on the Edge of Rejection:
========================

[?.?] Issue 39: clarifying default input sampling, which was classified as an extension issue
              (related to 22: clarifying meaning of unclocked, multi-cycle assertions, which was rejected)
Received on Tue Nov 23 08:15:22 2004