Extensions Group B - Discussion and Resolution

Results of discussion on 9 Nov 04:

Extensions Group B
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Issues (9,10,11,12)

9. Clarify definition of prev() at time 0:
Define the value of prev() in the first cycle, or define that it is not defined. [CE 2 Sep 04]

>> Should be aligned with SystemVerilog if possible. [JA 11Oct04]
>> Ensure conformity with SystemVerilog. [JM 11Oct04]

10. Clarify definitions of rose(), fell() at time 0:
If prev() is not defined in the first cycle, define the values of rose() and fell() in the first cycle. [CE 2 Sep 04]

>> Should be aligned with SystemVerilog if possible. [JA 11Oct04]
>> Ensure conformity with SystemVerilog. [JM 11Oct04]

11. Clarify definition of prev(v(i)):
Disallow prev(v(i)), where v is a vector and i is not a constant, or define which value of i should be used (the current value or the previous value). [CE 2 Sep 04]

>> Should surely be equivalent to (assume v(i) one bit wide): wire temp; assign temp = v(i); prev(temp). [JA 11Oct04]
>> Ensure conformity with SystemVerilog. [JM 11Oct04]

12. Clarify definition of prev(f(i)):
Disallow prev(f(i)), where f is a function and i is not a constant, or define which value of i should be used (the current value or the previous value). [CE 2 Sep 04]

>> See [comment about item] 11. [JA 11Oct04]
>> Ensure conformity with SystemVerilog. [JM 11Oct04]

Discussion
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- what does $past do in SV?
- in VHDL, s'last_value (prev(s)) at time 0 returns current value of s,
   for any parameter values of prev
- adopt the same for prev(s) at time 0
- check that this is consistent with $past in SV
- note that at the first tick of clk, prev(s,clk) = initial value of s

Resolution
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1. Prev(s) == initial value of s at time zero.

2. Prev(s,clk) == initial value of s at the first tick of clk

3. Given the definition of Prev(s), then unclocked rose/fell are False at time 0

4. Prev() should apply to all variables in the expression that is its argument,
    so prev(v(i)) means evaluate v(i) at the previous time point, and similarly
    prev(f(i)) means evaluate f(i) at the previous time point (i.e., given prev(i)
    as the input).

5. Note that if function f has side-effects (particularly, memory), then prev(f)
    may be undefined

6. In all of the above cases, we should check that this is consistent with
    SystemVerilog definitions
Received on Mon Nov 15 19:08:52 2004