Re: Extensions SC Agenda for Tues Nov 9

Erich,

I notice that issue 39 (sampling mechanism) is not in this list, though
according to the issues subcommittee minutes it was assigned to the extensions
committee.

Can I request that it be included, with a rider that the sampling mechanism
should be consistent with a standardized specification of the transition
system derived from a synthesized netlist?

Regards,

Anthony

Erich Marschner wrote:
>
> In the last WG meeting, we agreed that I should poll the working group regarding the relative size, or complexity, or the various extension proposals, so that we could use this information along with the priorities we have collected to decide the order in which we evaluate the proposals. I have been unable to accomplish this, due to a variety of distractions in the past 2 weeks. I suggest that we discuss this size issue briefly during the upcoming meeting.
>
> It was also suggested that we group the extensions proposals together, and that we announce ahead of time which group(s) will be discussed in each meeting, to give participants time to prepare. Cindy, Avigail, Sitvanit, and Dana have proposed the groupings below:
>
> group a: clocks - modeling layer: issues 7, 40
>
> group b: prev/rose/fell - corner cases: issues 9,10,11,12
>
> group c: vunits - binding, scoping, inheritance, parameterized vunits (for
> reusability): issues 5, 19, 23, 26, 30, 33
>
> group d: named constructs: issues 8, 38
>
> group e: simple subset: issue 13
>
> group f: vhdl: issues 15, 17, 27
>
> group g: abort: issue 20
>
> group h: portability: issue 21
>
> group i: forall: issues 25, 36, 41
>
> group j: non-determinism: issue 31
>
> group k: cover: issues 42, 43
>
> The items that were considered highest priority were issues 7,8,9,10,11,12,15,17, so in the Extensions SC meeting (immediately following the working group meeting) on Tuesday Nov 9, I propose that we plan to discuss the following groups as defined above:
>
> a (7,40) - default clock decls and endpoints, other decls, prev, etc.
> b (9,10,11,12) - defn of prev/rose/fell at time 0, and of prev(v(i)), prev(f(i))
>
> and if there is time,
>
> f (15, 17, 27) - booleans and built-in functions in VHDL
>
> In order to avoid getting bogged down on any one topic, I suggest that we spend at most 30 minutes on each group.
>
> Please review these issues and come to the meeting prepared to discuss them.
>
> Regards,
>
> Erich

-- 
Anthony McIsaac
STMicroelectronics (R&D) Limited
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