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IBIS FUTURES/COOKBOOK TASK GROUP MEETING MINUTES
Date: November 17, 2005

Attendees:
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Intel                   - Michael Mirmak, Arpad Muranyi
Mentor Graphics         - John Angulo, Ian Dodd
Micron                  - Randy Wolff
Teraspeed               - Bob Ross

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Next Meeting:
Thursday, December 1, 2005
9 AM - 10 AM US Pacific Time 

               Telephone     Bridge   Passcode
              916-356-2663     3      358-9732

Agenda:

9 - 9:10 AM        Opens
                   
9:10 - 9:30 AM     BIRD100 Comments (All)

9:30 - 9:55 AM     BIRD101 (Ross)

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No meeting was held November 24, due to US holidays.

Michael raised opens regardingin GEIA press releases, engineering
bulletins and other items.  Some discussion of the China summit and
DesignCon were held.

On BIRD100, Bob stated generally that he approves of the use of 
parentheses and also likes avoidance of direct mentions of Verilog-A.

Bob asked whether BIRD100 is needed for External Circuit?  There are some
D/A and A/D conversion port plus reserved names allowed for External Circuit
will BIRD100 work with them?  While you can write an External Circuit call
that uses reserved names, they are not required.  Ian noted that External
Circuit is being treated widely as a superset of External Model.  If
we want to do automatic delay measurement using External Circuits, the 
SI tool needs to know where to put the stimulus.  At present, the lack of
standard timing measurement locations in External Circuit is limiting
its adoption.  BIRD100 should not be limited by External Circuit concerns.

Ian further commented that the Verilog-A specification today is so far 
out of date that no one is actually using it or designing to it.  The 
Verilog-AMS specification is a Verilog-A superset, as no one restricts 
himself to Verilog-A anymore. 

Some scanning of Section 6b will be required to assure ourselves that
BIRD100 does not conflict with any of its provisions.  A parser revision 
will be needed but it will be somewhat trivial.  Bob suggested that adding
an example to the BIRD100 text might be necessary, for clarity.  

Michael asked about analog-only port names; are we limiting only the ports
or are we also limiting the content (internals) of the AMS code?  Digital 
signals could be used for timing analysis.

Ian suggests that Section 6b words do need "tweaking."  Michael asked whether
JEITA request for active filters can be supported using Verilog-A only.  Also, 
SystemVerilog is coming soon; should we support this under IBIS?  Arpad 
favors this option for IBIS 4.2, but Bob had unspecified concerns.