====================================================================== IBIS FUTURES/COOKBOOK TASK GROUP MEETING MINUTES Date: November 10, 2005 Attendees: ---------- Cadence Design Systems - Lance Wang Cisco Systems - Syed Huq Green Streak Programs - Lynne Green Intel - Michael Mirmak, Arpad Muranyi Mentor Graphics - John Angulo, Ian Dodd Micron - Randy Wolff ====================================================================== Next Meeting: Thursday, November 17, 2005 9 AM - 10 AM US Pacific Time Telephone Bridge Passcode 916-356-2663 1 733-5182 Agenda: 9 - 9:10 AM Opens 9:10 - 9:30 AM BIRD100 Comments (All) 9:30 - 9:55 AM BIRD101 (ICM-IBIS) Next Steps (Mirmak) ======================================================================== During Opens, Arpad and Ian noted that their Verilog-A support BIRD is almost complete. Can they post the BIRD before we go through all the changes possibly demanded by analysis of IBIS specification chapter 6B? The team noted no objection. To explan the BIRD, Arpad and Ian noted an ongoing a need for an analog-only support model to accommodate current tools. The macromodeling ibrary uses just the analog portions of VHDL-AMS and Verilog-AMS, plus it enables the SPICE-only crowd to translate the AMS blocks into SPICE primitives. Verilog-A is becoming increasingly available across tools. Perhaps Verilog-A can stand as a common analog modeling language (instead of pursuing a standard flavor of SPICE). Ian added that he told the library task group that their work was essentially illegal under the current spec, in the absence of direct support of analog-port-only models. Syed asked about Verilog-to-VHDL translators. The team noted that these are not now available nor are they likely to be possible. Ian and John observed that Mentor Graphics does not intend on abandoning VHDL-AMS in any way by supporting an analog-only option. Syed expressed concern about proliferation of options and standards. Trying to support several different language options might confuse the industry, causing "distraction" as mentioned by Mentor's Gary Pratt. Lynne noted that tool solutions today support analog-only AMS model configurations. Syed suggested that the main mission for IBIS should be to create enabling methods like S2IBIS2/3 to enable transition to AMS, as we enabled a transition from SPICE to IBIS. Arpad suggested that he will be getting the services of an intern or graduate student specifically for behavioral modeling, which may assist in tools development. To a certain extent, Arpad disputed that tools are moving away from SPICE; we should market on the basis that SPICE doesn't allow us to "get inside the simulation engine," while Verilog-A does. Michael asked about standard templates -- can we get templates for AMS solutions to general or common problems? Arpad responded that the Macromodeling Library Task Group has signed up for standard template component generation. Syed asked what happens if elements are used outside of the library context or used without reference to the libraries. This could cause confusion regarding the meaning of the elements. Syed suggested that standardization for the macromodeling library is not the way to go for the future. We need to be very clear about the IBIS usage model and intent for future applications. In the age of Verilog-A, the templates aren't needed and even Arpad doesn't like them. Lynne asked whether smaller companies supplying tools are willing to support Verilog-A. This could offer a compelling alternative to AMS support. The team settled on a simple message regarding the macromodeling library templates: no standardization in IBIS, or as a separate specification. The libraries will be positioned as an educational cookbook, or "training wheels" for getting to AMS-based languages. Syed suggested that the most compelling reason to use AMS is to enable authors to take advantage of all capabilities of the AMS languages without being limited to existing elements or structures. In closing, Michael reported that SystemVerilog was approved by the IEEE on Nov. 8.