====================================================================== IBIS FUTURES/COOKBOOK TASK GROUP MEETING MINUTES Date: October 20, 2005 Attendees: ---------- Cisco - Syed Huq, Zhiping Yang Intel - Michael Mirmak, Arpad Muranyi Mentor Graphics - John Angulo, Ian Dodd Sigrity - Sam Chitwood Teraspeed - Bob Ross ====================================================================== Next Meeting: Thursday, October 27, 2005 9 AM - 10 AM US Pacific Time Telephone Bridge Passcode 916-356-2663 2 673-6440 Agenda: 9 - 9:10 AM Opens 9:10 - 9:50 AM IBIS Spec. Next Steps (Mirmak) ======================================================================== During Opens, Michael raised the idea of changing the Futures meeting schedule, reducing the meeting schedule to either to 1 hour every week OR 2 hours every other week. Arpad commented that shorter but more frequent meetings are preferable. Bob agreed, but noted that two week intervals may make the effect of reduced attendance more negative. Arpad added that we "slow down" progress with 2-week meetings. Power Delivery and Loop Inductance ---------------------------------- Michael presented his final summary of results on loop inductance. With proper node connections and optimized simulator settings, a difference in the nanovolts can be achieved between the receiver voltages measured for circuits with matched loop inductances but different inductor values. Michael noted that transmission line simulations had not yet been performed. Bob suggested that, as an ideal transmission line is a myth, adding one will compromise our voltage analysis. Michael asked about model reduction, where non-ideal return paths are concatenated into one idealized path. Is this legitimate? Sam noted that what the team is doing is a simplified, easy example. No frequency dependence included here, nor are other more realistic system effects. As more realism is added a perfect match will be harder to achieve. Bob suggested that the industry needs an ideal transmission line case to show that the loop inductance concept can apply to BIRD95. Zhiping commented that, if one does not have ground parasitics and uses an ideal ground for a transmission line reference, convergence becomes difficult. Unfortunately, such a case is not realistic. He asked whether transmission line equivalence under ideal conditions is good enough? He will send out references on model reduction (assuming total current into block = total current out of block) to show its application to the BIRD95 discussion. Gate modulation --------------- Arpad noted that no work has been recently performed on the project, as Antonio hasn't responded to Arpad's latest phase delay slides. IBIS Next Steps --------------- Michael raised the issue of the next steps for IBIS, particularly as BIRDs are "piling up" without a plan for the next specification to be released. Michael verbally listed out the big changes still pending: BIRD95, BIRD74, IBIS-ICM links and user-defined measurements, plus supporting [External Model] under [Circuit Call]. Bob suggested that add a new [Model Call] keyword might make this easier. John Angulo to analyze. Bob noted that 10 BIRDs are approved for "specification cleanup," with the additional problem of "inoperative text" in IBIS 4.1 (Fig. 12 implication of ICM) that should also be cleaned up. We could release BIRD95 separately (IBIS 4.3). In general, our choices include: 1) Close out IBIS 4.2 with 10 BIRDs today 2) Update parser with 40 character model name extension 3) Release IBIS 4.2, with work in parallel and following on 5.0 Syed asked whether any restriction or definition exists on how IBIS 4.3 could be defined. None was identified. Ian noted that EDA tools in the industry are still playing "catch up" to IBIS improvements. We need standardization (EIA, ANSI, etc.) for a benchmark. Syed asked for a summary of the small versus large changes anticipated in the specification; Michael to provide in a separate presentation John noted that money is a problem for parser payments, as we are not expecting new parser development income until IBIS 5.0 development starts. Ian added that, in general, BIRD95 may not be a problem for inclusion in 4.2 *and* standardization, though the parser support is not trivial. Separately, Ian asked whether IBIS 4.1 can be extended to support Verilog-A explicitly. Arpad says this may not be needed, as Verilog-A is explicitly now the analog portion of Verilog-AMS. Will D/A, A/D converters be required for Verilog-A? Do we need a new "language" subparameter entry? Ian to resolve a recommendation with Arpad. ARs ----- Michael Mirmak - add conclusion slide to presentation on loop inductance Michael Mirmak - provide simplified BIRD100 proposal John Angulo - look into exact spec. changes for [External Model] under [Circuit Call] Michael Mirmak - put slides together showing options on IBIS 4.2 and 5.0 -- DONE John Angulo - analyze BIRD100 proposals, after Mentor discussion Sam Chitwood - analyze BIRD100 proposals, after Sigrity discussion Lance Wang - analyze BIRD100 proposals, after Cadence discussion