====================================================================== IBIS FUTURES/COOKBOOK TASK GROUP MEETING MINUTES Date: October 6, 2005 Attendees: ---------- Cadence Design Systems - Lance Wang, Shangli Wu Cisco - Zhiping Yang, Vinu Arumugham Intel - Michael Mirmak, Arpad Muranyi Mentor Graphics - Ian Dodd Micron - Randy Wolff NCSU - Ambrish Varma Sigrity - Sam Chitwood Teraspeed - Bob Ross ====================================================================== Next Meeting: Thursday, October 13, 2005 9 AM - 11 AM US Pacific Time Telephone Bridge Passcode 916-356-2663 1 740-2249 Agenda: 9 - 9:10 AM Opens 9:10 - 9:35 AM Power Delivery Topics - New case comparisons (Mirmak) 9:35 - 10 AM IBIS Spec. Next Steps ======================================================================== FUTURES --------- Michael summarized the latest work. The comparison cases for various loop inductances were regenerated. Arpad suggests that the differences are less than one-tenth of 1%. Michael expressed some concerns that the differences are not exactly zero. Ambrish stated that electrical circuit theory demands that if no ground inductance is present, then mutuals must be. Our BIRD95 tests using the Micron models don't have mututals either. Zhiping suggests that mutuals aren't necessary. When we talk about mutual terms, we are talking about loop concept. Maintain all the loop inductances as equivalent and results should also be equivalent. Ambrish asked whether we aren't trying to duplicate package parasitics. Sam suggested this might be a bogus assumption, particularly in this test case set (with no ground parasitics on the transmission line references, for example). Again, if the loops are accurate, the individual parts can be any values we want. Bob suggests transmission line referencing is messing up the current flow and causing the inaccuracies noted by Michael. Zhiping suggests (1) changing inductance terms to reduce truncation in the mutual value and (2) removing the transmission line. Lance presented two sets of slides. His first tested a driver in a low state connected to local ground; power connected to Vcc. He noted that "GND" was not the actual ground circuit name. The power supply is tied to ideal ground, not buffer ground. Lance's case show perfect overlay for 50/50 and 25/75 C_comp proportions. Lance suggests the transistor model may be complex enough to make IBIS assumptions invalid. Zhiping asked whether ideal ground used for the VDD. Leakage currents could result if ideal ground is used. Our simulations can't have global nodes in the SPICE circuit. Vinu requested that output plots be generated for all the nodes versus local die ground node. Zhiping asked that the ideal node be removed from Lance's circuit, as core power Vddq is biased using die power vs. ideal ground instead of local ground. Lance's second presentation expressed Cadence's view on BIRD95. All EDA vendors need formal scientific proofs to implement actual calculations. The formal proof of BIRD95 is unclear. IBIS needs a complete PDS solution, and BIRD95 is only part of it. Further, I/T tables are immeasurable. How can you isolate buffer and package parasitics, we asked. In addition, do all inductances for the total loops need to be in the "top" (in the supply path)? Arpad suggests this was never the implication. Lance's presentation on new proposal: using IEEE paper equations, he derives additional elements expressing partial derivatives of current with respect to voltage to add to IBIS 2.1 base data. Zhiping mentioned that crossbar current is not mentioned. Bob added that C_comp terms are missing. Lance suggests that BIRD95 is a specific solution of the Cadence solution general case. Syed responded that, therefore, the Cadence proposal is BIRD97+95 without separating BIRD95 out. Lance confirmed this. Arpad and Lance discussed the "phase delay" problem, where changes in the slope of the power supply rail appear on the output of the transistor-level driver model. Internal to the buffer, there are capacitances around the pre-driver. When you change the supply in a DC sense, changes are not noticeable. However, the AC effects from the voltage slope will "show up" on the output. In an AC sense, the gate voltage will go to "other places" before it settles to the DC value. The output will not respond directly in proportion to the DC voltage. How do we characterize this delay? Arpad hasn't thought up an initial test cases. "Phase delay" comes from the sine response used to identify it. ARs ----- Michael Mirmak - update drawing with node names -- DONE Lance Wang - for phase delay issue, update sim buffer stimulus to transition only from 1.8 to 1.7 and "go horizontal"; sweep slope and watch output response; -- DONE update decks to show sources and loads referenced to local ground -- DONE John Angulo - analyze BIRD100 proposals, after Mentor discussion Sam Chitwood - analyze BIRD100 proposals, after Sigrity discussion Lance Wang - analyze BIRD100 proposals, after Cadence discussion