-- -------------------------------------------------------------------- --Copyright©2003 by the Institute of Electrical and Electronics Engineers, Inc. -- Three Park Avenue -- New York, NY 10016-5997, USA -- All rights reserved. -- -- This document is an unapproved draft of a proposed IEEE Standard. As such, -- this document is subject to change. USE AT YOUR OWN RISK! Because this -- is an unapproved draft, this document must not be utilized for any -- conformance/compliance purposes. Permission is hereby granted for IEEE -- Standards Committee participants to reproduce this document for purposes -- of IEEE standardization activities only. Prior to submitting this document -- to another standards development organization for standardization -- activities, permission must first be obtained from the Manager, Standards -- Licensing and Contracts, IEEE Standards Activities Department. Other -- entities seeking permission to reproduce this document, in whole or in -- part, must obtain permission from the Manager, Standards Licensing and -- Contracts, IEEE Standard Activities Department. -- -- IEEE Standards Activities Department -- Standards Licensing and Contracts -- 445 Hoes Lane, P.O. Box 1331 -- Piscataway, NJ 08855-1331, USA -- -- Title : FPHDL_EA < IEEE std # 1076.3 > -- -- Library : This package shall be compiled into a library -- symbolically named IEEE. -- -- Developers: IEEE DASC FPHDL Working Group, PAR 1076.3 -- -- Purpose : Floating point HDL entity architecture wrappers, -- needed for Verilog cosimulation. Generics are -- used to pass all size parameters. -- -- Limitation: -- -- -------------------------------------------------------------------- -- modification history : Last Modified $Date: 2004-01-06 09:17:37-05 $ -- Version $Id: fphdl_ea.vhd,v 1.7 2004-01-06 09:17:37-05 bishop Exp $ -- -------------------------------------------------------------------- -- $Log: fphdl_ea.vhd,v $ -- Revision 1.7 2004-01-06 09:17:37-05 bishop -- Added cbrt and exp functions (don't need write functions here) -- -- Revision 1.6 2003-10-20 14:54:56-04 bishop -- Added a check_error parameter -- -- Revision 1.5 2003-07-29 15:35:47-04 bishop -- Added oneoverx, dividebyp2, polar_to_complex and complex_to_polar functions -- -- Revision 1.4 2003-05-22 13:55:27-04 bishop -- Added a oneoverx routine -- -- Revision 1.3 2003-01-23 16:28:14-05 bishop -- Fixed the std_ulogic_vector conversion function -- -- Revision 1.2 2003-01-17 14:21:45-05 bishop -- Fixed several problems with bit width matching -- -- Revision 1.1 2003-01-15 09:00:02-05 bishop -- Initial revision -- -- -------------------------------------------------------------------- -- Author David Bishop (dbishop@vhdl.org) library ieee; use ieee.std_logic_1164.all; use work.fphdl_base_pkg.all; package fphdl_ea_pkg is constant fraction_width_default : integer := 23; -- default fraction constant exponent_width_default : integer := 8; -- default exponent constant ieee_extend_default : integer := 1; -- default to true constant check_error_default : integer := 1; -- check error constant round_style_default : integer := 0; -- default to "round_nearest" constant integer_width_default : integer := 32; -- normal integer function fp_to_sulv ( result_fp : floating_point) -- fp number w/ negative index return std_ulogic_vector; end package fphdl_ea_pkg; package body fphdl_ea_pkg is function fp_to_sulv ( result_fp : floating_point) -- fp number w/ negative index return std_ulogic_vector is variable result_sulv : std_ulogic_vector (result_fp'high - result_fp'low downto 0); begin floop : for i in result_sulv'range loop result_sulv (i) := result_fp (i + result_fp'low); end loop floop; return result_sulv; end function fp_to_sulv; end package body fphdl_ea_pkg; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity absolute_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity absolute_ea; use work.fphdl_base_pkg.all; architecture struct of absolute_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result begin arg_fp <= floating_point(arg); result_fp <= absolute (arg => arg_fp); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity negative_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity negative_ea; use work.fphdl_base_pkg.all; architecture struct of negative_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result begin arg_fp <= floating_point(arg); result_fp <= negative (arg => arg_fp); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity addition_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity addition_ea; use work.fphdl_base_pkg.all; architecture struct of addition_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point (l); r_fp <= floating_point (r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= addition (l => l_fp, r => r_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity complex_add_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res_r : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output res_i : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.r l_i : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.i r_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- r.r r_i : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- r.i end entity complex_add_ea; use work.fphdl_base_pkg.all; architecture struct of complex_add_ea is signal l_r_fp, l_i_fp, r_r_fp, r_i_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin -- complex_add_ea l_r_fp <= floating_point(l_r); l_i_fp <= floating_point(l_i); r_r_fp <= floating_point(r_r); r_i_fp <= floating_point(r_i); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); -- purpose: process needed because procedure are vairables -- type : combinational -- inputs : l_r, l_i, r_r, r_i -- outputs: res_r, res_i run_proc : process (l_r_fp, l_i_fp, r_r_fp, r_i_fp ) is variable result_real, result_complex : floating_point (exponent_width downto -fraction_width); -- real and imaginary portions begin -- process run_proc complex_add (l_real => l_r_fp, l_complex => l_i_fp, r_real => r_r_fp, r_complex => r_i_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend, result_real => result_real, result_complex => result_complex); res_r <= fp_to_sulv (result_real); res_i <= fp_to_sulv (result_complex); end process run_proc; end struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity subtract_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity subtract_ea; use work.fphdl_base_pkg.all; architecture struct of subtract_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= subtract ( l => l_fp, r => r_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity complex_subtract_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res_r : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output res_i : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.r l_i : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.i r_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- r.r r_i : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- r.i end entity complex_subtract_ea; use work.fphdl_base_pkg.all; architecture struct of complex_subtract_ea is signal l_r_fp, l_i_fp, r_r_fp, r_i_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin -- complex_subtract_ea l_r_fp <= floating_point(l_r); l_i_fp <= floating_point(l_i); r_r_fp <= floating_point(r_r); r_i_fp <= floating_point(r_i); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); -- purpose: process needed because procedure are vairables -- type : combinational -- inputs : l_r, l_i, r_r, r_i -- outputs: res_r, res_i run_proc : process (l_r_fp, l_i_fp, r_r_fp, r_i_fp ) is variable result_real, result_complex : floating_point (exponent_width downto -fraction_width); -- real and imaginary portions begin -- process run_proc complex_subtract (l_real => l_r_fp, l_complex => l_i_fp, r_real => r_r_fp, r_complex => r_i_fp, round_style => fp_round_style, ieee_extend => fp_ieee_extend, result_real => result_real, result_complex => result_complex); res_r <= fp_to_sulv (result_real); res_i <= fp_to_sulv (result_complex); end process run_proc; end struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity multiply_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity multiply_ea; use work.fphdl_base_pkg.all; architecture struct of multiply_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= multiply ( l => l_fp, r => r_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity complex_multiply_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res_r : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output res_i : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.r l_i : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.i r_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- r.r r_i : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- r.i end entity complex_multiply_ea; use work.fphdl_base_pkg.all; architecture struct of complex_multiply_ea is signal l_r_fp, l_i_fp, r_r_fp, r_i_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin -- complex_multiply_ea l_r_fp <= floating_point(l_r); l_i_fp <= floating_point(l_i); r_r_fp <= floating_point(r_r); r_i_fp <= floating_point(r_i); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); -- purpose: process needed because procedure are vairables -- type : combinational -- inputs : l_r, l_i, r_r, r_i -- outputs: res_r, res_i run_proc : process (l_r_fp, l_i_fp, r_r_fp, r_i_fp ) is variable result_real, result_complex : floating_point (exponent_width downto -fraction_width); -- real and imaginary portions begin -- process run_proc complex_multiply (l_real => l_r_fp, l_complex => l_i_fp, r_real => r_r_fp, r_complex => r_i_fp, round_style => fp_round_style, ieee_extend => fp_ieee_extend, result_real => result_real, result_complex => result_complex); res_r <= fp_to_sulv (result_real); res_i <= fp_to_sulv (result_complex); end process run_proc; end struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity divide_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity divide_ea; use work.fphdl_base_pkg.all; architecture struct of divide_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= divide ( l => l_fp, r => r_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity oneoverx_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity oneoverx_ea; use work.fphdl_base_pkg.all; architecture struct of oneoverx_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= onedivx ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity dividebyp2_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity dividebyp2_ea; use work.fphdl_base_pkg.all; architecture struct of dividebyp2_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= divisionbyp2 ( l => l_fp, r => r_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity complex_divide_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res_r : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output res_i : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.r l_i : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.i r_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- r.r r_i : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- r.i end entity complex_divide_ea; use work.fphdl_base_pkg.all; architecture struct of complex_divide_ea is signal l_r_fp, l_i_fp, r_r_fp, r_i_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin -- complex_divide_ea l_r_fp <= floating_point(l_r); l_i_fp <= floating_point(l_i); r_r_fp <= floating_point(r_r); r_i_fp <= floating_point(r_i); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); -- purpose: process needed because procedure are vairables -- type : combinational -- inputs : l_r, l_i, r_r, r_i -- outputs: res_r, res_i run_proc : process (l_r_fp, l_i_fp, r_r_fp, r_i_fp ) is variable result_real, result_complex : floating_point (exponent_width downto -fraction_width); -- real and imaginary portions begin -- process run_proc complex_divide (l_real => l_r_fp, l_complex => l_i_fp, r_real => r_r_fp, r_complex => r_i_fp, round_style => fp_round_style, ieee_extend => fp_ieee_extend, result_real => result_real, result_complex => result_complex); res_r <= fp_to_sulv (result_real); res_i <= fp_to_sulv (result_complex); end process run_proc; end struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity complex_to_polar_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res_mag : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output res_angle : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg_r : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.r arg_i : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- l.i end entity complex_to_polar_ea; use work.fphdl_base_pkg.all; architecture struct of complex_to_polar_ea is signal arg_r_fp, arg_i_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin -- complex_divide_ea arg_r_fp <= floating_point(arg_r); arg_i_fp <= floating_point(arg_i); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); -- purpose: process needed because procedure are vairables -- type : combinational -- inputs : l_r, l_i, r_r, r_i -- outputs: res_r, res_i run_proc : process (arg_r_fp, arg_i_fp ) is variable result_mag, result_angle : floating_point (exponent_width downto -fraction_width); -- real and imaginary portions begin -- process run_proc complex_to_polar (arg_real => arg_r_fp, arg_complex => arg_i_fp, round_style => fp_round_style, ieee_extend => fp_ieee_extend, result_mag => result_mag, result_angle => result_angle); res_mag <= fp_to_sulv (result_mag); res_angle <= fp_to_sulv (result_angle); end process run_proc; end struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity polar_to_complex_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res_r : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output res_i : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg_mag : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- l.r arg_angle : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- l.i end entity polar_to_complex_ea; use work.fphdl_base_pkg.all; architecture struct of polar_to_complex_ea is signal arg_mag_fp, arg_ang_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin -- complex_divide_ea arg_mag_fp <= floating_point(arg_mag); arg_ang_fp <= floating_point(arg_angle); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); -- purpose: process needed because procedure are vairables -- type : combinational -- inputs : l_r, l_i, r_r, r_i -- outputs: res_r, res_i run_proc : process (arg_mag_fp, arg_ang_fp ) is variable result_real, result_imaginary : floating_point (exponent_width downto -fraction_width); -- real and imaginary portions begin -- process run_proc polar_to_complex (arg_mag => arg_mag_fp, arg_angle => arg_ang_fp, round_style => fp_round_style, ieee_extend => fp_ieee_extend, result_real => result_real, result_complex => result_imaginary); res_r <= fp_to_sulv (result_real); res_i <= fp_to_sulv (result_imaginary); end process run_proc; end struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity remainder_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity remainder_ea; use work.fphdl_base_pkg.all; architecture struct of remainder_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= remainder ( l => l_fp, r => r_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity square_root_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity square_root_ea; use work.fphdl_base_pkg.all; architecture struct of square_root_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= square_root ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity cube_root_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity cube_root_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of cube_root_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= cube_root ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity expone_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity expone_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of expone_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= expone ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity log_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output base : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- integer arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity log_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of log_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal base_int : floating_point (exponent_width downto -fraction_width); -- base in integer format signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); base_int <= floating_point(base); result_fp <= logarithm ( base => base_int, arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity natural_log_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity natural_log_ea; use work.fphdl_base_pkg.all; architecture struct of natural_log_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= natural_log ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity power_of_fp_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity power_of_fp_ea; use work.fphdl_base_pkg.all; architecture struct of power_of_fp_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= power_of ( l => l_fp, r => r_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity power_of_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output l : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- arguments r : in std_ulogic_vector(31 downto 0)); end entity power_of_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of power_of_ea is signal l_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal r_int : integer; -- base in integer format signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_int <= to_integer (signed (r)); result_fp <= power_of ( l => l_fp, r => r_int, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; ----------------------------------------------------------------------------- -- Angle functions -- sine, cosine, tangent, arc_sine, arc_cosine, arc_tangent library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity sine_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity sine_ea; use work.fphdl_base_pkg.all; architecture struct of sine_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= sine ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity cosine_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity cosine_ea; use work.fphdl_base_pkg.all; architecture struct of cosine_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= cosine ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity tangent_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity tangent_ea; use work.fphdl_base_pkg.all; architecture struct of tangent_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= tangent ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity arc_sine_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity arc_sine_ea; use work.fphdl_base_pkg.all; architecture struct of arc_sine_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= arc_sine ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity arc_cosine_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity arc_cosine_ea; use work.fphdl_base_pkg.all; architecture struct of arc_cosine_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= arc_cosine ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity arc_tangent_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity arc_tangent_ea; use work.fphdl_base_pkg.all; architecture struct of arc_tangent_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); result_fp <= arc_tangent ( arg => arg_fp, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; -- compare functions library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity equal_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity equal_ea; use work.fphdl_base_pkg.all; architecture struct of equal_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal is_equal, is_unordered : boolean; signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); is_equal <= equal ( l => l_fp, r => r_fp); is_unordered <= fp_Unordered (x => l_fp, y => r_fp) when fp_check_error else false; res <= '1' when (is_equal and not is_unordered) else '0'; end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity not_equal_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity not_equal_ea; use work.fphdl_base_pkg.all; architecture struct of not_equal_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal is_equal, is_unordered : boolean; signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); fp_ieee_extend <= (ieee_extend > 0); fp_round_style <= round_type'val(round_style); is_equal <= equal ( l => l_fp, r => r_fp); is_unordered <= fp_Unordered (x => l_fp, y => r_fp) when (check_error > 0) else false; res <= '1' when (is_equal and not is_unordered) else '0'; end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity greater_than_or_equal_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity greater_than_or_equal_ea; use work.fphdl_base_pkg.all; architecture struct of greater_than_or_equal_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal is_less_than, is_unordered : boolean; begin l_fp <= floating_point(l); r_fp <= floating_point(r); is_less_than <= less_than ( l => l_fp, r => r_fp); is_unordered <= fp_Unordered (x => l_fp, y => r_fp) when (check_error > 0) else false; res <= '1' when (not is_less_than and not is_unordered) else '0'; end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity less_than_or_equal_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity less_than_or_equal_ea; use work.fphdl_base_pkg.all; architecture struct of less_than_or_equal_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal is_greater_than, is_unordered : boolean; signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); is_greater_than <= greater_than ( l => l_fp, r => r_fp); is_unordered <= fp_Unordered (x => l_fp, y => r_fp) when (check_error > 0) else false; res <= '1' when (not is_greater_than and not is_unordered) else '0'; end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity greater_than_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity greater_than_ea; use work.fphdl_base_pkg.all; architecture struct of greater_than_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal is_greater_than, is_unordered : boolean; begin l_fp <= floating_point(l); r_fp <= floating_point(r); is_greater_than <= greater_than ( l => l_fp, r => r_fp); is_unordered <= fp_Unordered (x => l_fp, y => r_fp) when (check_error > 0) else false; res <= '1' when (is_greater_than and not is_unordered) else '0'; end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity less_than_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output l, r : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity less_than_ea; use work.fphdl_base_pkg.all; architecture struct of less_than_ea is signal l_fp, r_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal is_less_than, is_unordered : boolean; signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin l_fp <= floating_point(l); r_fp <= floating_point(r); is_less_than <= less_than ( l => l_fp, r => r_fp); is_unordered <= fp_Unordered (x => l_fp, y => r_fp) when (check_error > 0) else false; res <= '1' when (is_less_than and not is_unordered) else '0'; end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity integer_to_fp_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (31 downto 0)); -- integer end entity integer_to_fp_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of integer_to_fp_ea is signal arg_int : integer; -- integer version of input signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_round_style : round_type; -- Round style begin fp_ieee_extend <= (ieee_extend > 0); fp_round_style <= round_type'val(round_style); arg_int <= to_integer (signed(arg)); result_fp <= to_floating_point ( arg => arg_int, fraction_width => fraction_width, exponent_width => exponent_width, round_style => fp_round_style); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity real_to_fp_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (63 downto 0)); -- real end entity real_to_fp_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of real_to_fp_ea is signal arg_fp : floating_point (11 downto -52); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); -- Verilog real numbers are actually 64 bit floating point. result_fp <= resize_floating_point ( arg => arg_fp, fraction_width => fraction_width, exponent_width => exponent_width, ieee_extend_in => true, round_style => fp_round_style, ieee_extend => fp_ieee_extend); res <= fp_to_sulv ( result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity unsigned_to_fp_ea is generic ( size : integer := integer_width_default; -- high bit fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (size-1 downto 0)); -- arguments end entity unsigned_to_fp_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of unsigned_to_fp_ea is signal arg_unsigned : unsigned (arg'range); -- unsigned signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_round_style : round_type; -- Round style begin fp_ieee_extend <= (ieee_extend > 0); fp_round_style <= round_type'val(round_style); arg_unsigned <= unsigned (arg); result_fp <= to_floating_point ( arg => arg_unsigned, fraction_width => fraction_width, exponent_width => exponent_width, round_style => fp_round_style); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity signed_to_fp_ea is generic ( size : integer := integer_width_default; -- high bit fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output arg : in std_ulogic_vector (size-1 downto 0)); -- arguments end entity signed_to_fp_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of signed_to_fp_ea is signal arg_signed : signed (arg'range); -- unsigned signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_round_style : round_type; -- Round style begin fp_round_style <= round_type'val(round_style); arg_signed <= signed (arg); result_fp <= to_floating_point ( arg => arg_signed, fraction_width => fraction_width, exponent_width => exponent_width, round_style => fp_round_style); res <= fp_to_sulv (result_fp); end architecture struct; -- purpose: Convertes a 32 bit floating point into an unsigned library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity fp_to_unsigned_ea is generic ( size : integer := integer_width_default; -- high bit fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (size-1 downto 0); -- unsigned output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- input end entity fp_to_unsigned_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of fp_to_unsigned_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal res_unsigned : unsigned (res'range); -- unsigned signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_round_style <= round_type'val(round_style); res_unsigned <= fp_to_unsigned ( arg => arg_fp, size => size, round_style => fp_round_style); res <= std_ulogic_vector (res_unsigned); end architecture struct; -- purpose: Convertes a 32 bit floating point into an signed library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity fp_to_signed_ea is generic ( size : integer := integer_width_default; -- high bit fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (size-1 downto 0); -- signed output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- input end entity fp_to_signed_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of fp_to_signed_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal res_signed : signed (res'range); -- unsigned signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_round_style <= round_type'val(round_style); res_signed <= fp_to_signed ( arg => arg_fp, size => size, round_style => fp_round_style); res <= std_ulogic_vector (res_signed); end architecture struct; -- purpose: Convertes a 32 bit floating point into an unsigned library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity fp_to_real_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (63 downto 0); -- Verilog fp output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- input end entity fp_to_real_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of fp_to_real_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (11 downto -52); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_ieee_extend <= (ieee_extend > 0); fp_round_style <= round_type'val(round_style); -- Verilog real numbers are actually 64 bit floating point. result_fp <= resize_floating_point ( arg => arg_fp, fraction_width => 52, exponent_width => 11, -- 64 bit exponent ieee_extend_in => fp_ieee_extend, round_style => round_nearest, ieee_extend => true); res <= fp_to_sulv ( result_fp); end architecture struct; -- purpose: Convertes a 32 bit floating point into an unsigned library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity fp_to_integer_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (31 downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity fp_to_integer_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of fp_to_integer_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_int : integer; -- result signal fp_round_style : round_type; -- Round style begin arg_fp <= floating_point(arg); fp_round_style <= round_type'val(round_style); result_int <= fp_to_integer ( arg => arg_fp, round_style => fp_round_style); res <= std_ulogic_vector ( to_signed (result_int, res'high +1)); end architecture struct; ----------------------------------------------------------------------------- -- Recommended Functions from the IEEE 754 Appendix ----------------------------------------------------------------------------- -- returns x with the sign of y. library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Copysign_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output x, y : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity Copysign_ea; use work.fphdl_base_pkg.all; architecture struct of Copysign_ea is signal x_fp, y_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_round_style : round_type; -- Round style begin x_fp <= floating_point(x); y_fp <= floating_point(y); result_fp <= fp_Copysign ( x => x_fp, y => y_fp); res <= fp_to_sulv (result_fp); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Scalb_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output y : in std_ulogic_vector (fraction_width+exponent_width downto 0); -- arguments n : in std_ulogic_vector (31 downto 0)); end entity Scalb_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of Scalb_ea is signal y_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal N_int : integer; -- base in integer format signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking signal fp_round_style : round_type; -- Round style begin -- Returns y * 2**n for intergral values of N without computing 2**n y_fp <= floating_point(y); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_round_style <= round_type'val(round_style); N_int <= to_integer (unsigned (n)); result_fp <= fp_Scalb (y => y_fp, N => N_int, round_style => fp_round_style, check_error => fp_check_error, ieee_extend => fp_ieee_extend); res <= fp_to_sulv (result_fp); end architecture struct; -- returns the unbiased exponent of x library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Logb_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (31 downto 0); -- output arg : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity Logb_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of Logb_ea is signal arg_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal resint : integer; -- result as integer begin arg_fp <= floating_point(arg); resint <= fp_Logb ( x => arg_fp); res <= std_ulogic_vector (to_signed (resint, res'high +1)); end architecture struct; -- returns the unbiased exponent of x -- function Logb ( -- x : fp32) -- floating point input -- return signed is -- begin -- return fp_Logb ( x => floating_point (x), -- length => fp_length, -- exponent => fp_exponent); -- end Logb; -- returns the next represtable neighbor of x in the direction toward y library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Nextafter_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (fraction_width+exponent_width downto 0); -- output x, y : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity Nextafter_ea; use work.fphdl_base_pkg.all; architecture struct of Nextafter_ea is signal x_fp, y_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal result_fp : floating_point (exponent_width downto -fraction_width); -- result signal fp_ieee_extend : boolean; -- Use denormal numbers signal fp_check_error : boolean; -- Turn on error checking begin x_fp <= floating_point(x); y_fp <= floating_point(y); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); result_fp <= fp_Nextafter ( x => x_fp, y => y_fp, check_error => fp_check_error, ieee_extend => fp_ieee_extend ); res <= fp_to_sulv (result_fp); end architecture struct; -- Returns true if +/- infinity library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Finite_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output x : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity Finite_ea; use work.fphdl_base_pkg.all; architecture struct of Finite_ea is signal x_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_state : valid_fpstate; -- fp state begin x_fp <= floating_point(x); fp_state <= fp_Class (x => x_fp); res <= '1' when (( fp_state = infinity ) or (fp_state = neg_inf)) else '0'; end architecture struct; -- Returns true if NaN (Not a Number) library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Isnan_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output x : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity Isnan_ea; use work.fphdl_base_pkg.all; architecture struct of Isnan_ea is signal x_fp : floating_point (exponent_width downto -fraction_width); -- argument signal fp_state : valid_fpstate; -- fp state begin x_fp <= floating_point(x); fp_state <= fp_class (x => x_fp); res <= '1' when (( fp_state = nan ) or (fp_state = quiet_nan)) else '0'; end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Class_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic_vector (3 downto 0); -- vectorized state of class x : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- argument end entity Class_ea; library ieee; use ieee.numeric_std.all; use work.fphdl_base_pkg.all; architecture struct of Class_ea is signal x_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal fp_state : valid_fpstate; -- fp state signal statepos : integer; -- integer version of state signal fp_check_error : boolean; -- Turn on error checking signal fp_ieee_extend : boolean; -- Use denormal numbers begin -- architecture struct x_fp <= floating_point(x); fp_ieee_extend <= (ieee_extend > 0); fp_check_error <= (check_error > 0); fp_state <= fp_class (x => x_fp, check_error => fp_check_error); statepos <= valid_fpstate'pos(fp_state); res <= std_ulogic_vector(to_unsigned(statepos, 4)); end architecture struct; library ieee; use ieee.std_logic_1164.all; use work.fphdl_ea_pkg.all; entity Unordered_ea is generic ( fraction_width : integer := fraction_width_default; -- fraction exponent_width : integer := exponent_width_default; -- exponent check_error : integer := check_error_default; -- true ieee_extend : integer := ieee_extend_default; -- true round_style : integer := round_style_default); -- round_nearest port ( res : out std_ulogic; -- output x, y : in std_ulogic_vector (fraction_width+exponent_width downto 0)); -- arguments end entity Unordered_ea; use work.fphdl_base_pkg.all; architecture struct of Unordered_ea is signal x_fp, y_fp : floating_point (exponent_width downto -fraction_width); -- fp versions signal res_boolean : boolean; -- result as boolean begin x_fp <= floating_point(x); y_fp <= floating_point(y); res_boolean <= fp_Unordered (x => x_fp, y => y_fp); res <= '1' when res_boolean else '0'; end architecture struct;