/* --------------------------------------------------------------------
--
--
-- Copyright©2002 by the Institute of Electrical and Electronics Engineers, Inc.
-- Three Park Avenue
-- New York, NY 10016-5997, USA
-- All rights reserved.
-- 
-- This document is an unapproved draft of a proposed IEEE Standard. As such,
-- this document is subject to change. USE AT YOUR OWN RISK! Because this
--  is an unapproved draft, this document must not be utilized for any 
-- conformance/compliance purposes. Permission is hereby granted for IEEE 
-- Standards Committee participants to reproduce this document for purposes 
-- of IEEE standardization activities only. Prior to submitting this document 
-- to another standards development organization for standardization 
-- activities, permission must first be obtained from the Manager, Standards 
-- Licensing and Contracts, IEEE Standards Activities Department. Other 
-- entities seeking permission to reproduce this document, in whole or in 
-- part, must obtain permission from the Manager, Standards Licensing and 
-- Contracts, IEEE Standard Activities Department.
--
-- IEEE Standards Activities Department
-- Standards Licensing and Contracts
-- 445 Hoes Lane, P.O. Box 1331
-- Piscataway, NJ 08855-1331, USA
--
--   Title     :  FPHDL_PKG < IEEE std # 1076.3 >
--
--   Developers:  VHDL Synthesis working group, PAR 1076.3
--
--   Purpose   :  This version of the Verilog packages uses the 
--                verilog real type. Converted from fphdl64_pkg.v
--                and fphdl64_ea.vhd  by Kurt Baty
--
--   Limitation:  Dependant on "fphdl64real_functions.inc".
--
-- --------------------------------------------------------------------
--   Last Modified $Date: 2003-01-15 09:35:51-05 $  $Id: fphdl64_real_pkg.v,v 1.4 2003-01-15 09:35:51-05 bishop Exp $
--   $Log: fphdl64_real_pkg.v,v $
--   Revision 1.4  2003-01-15 09:35:51-05  bishop
--   1/15/2003 update
--
--   Revision 1.3  2003-01-03 13:06:25-05  bishop
--   Added trig functions
--   modified name of include file
--
--   Revision 1.2  2003-01-02 09:44:59-05  bishop
--   Added the .inc dependancy under "Limitations".
--
--   Revision 1.1  2003-01-02 09:41:23-05  bishop
--   Initial revision
--
-- --------------------------------------------------------------------
*/

module fp64_abs (res, arg); // absolute number
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = absolute(arg);
endmodule // fp64_abs

module fp64_neg (res, arg); // unary negative
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = negative(arg);
endmodule // fp64_neg

module fp64_add (res, l, r); // addition (l + r)
   output [63:0] res;
   input [63:0] l, r;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = addition(l,r);
endmodule // fp64_add

module fp64_add_c (res_r, res_i, l_r, l_i, r_r, r_i); // complex add
   output [63:0] res_r, res_i;
   input [63:0] l_r, l_i, r_r, r_i;
   wire	[63:0]	res_r, res_i;
`include "fphdl64_real_functions_base.inc"
   assign {res_r, res_i} = complex_add(l_r, l_i, r_r, r_i);
endmodule // fp64_add_c

module fp64_sub (res, l, r); // subtraction (l - r)
   output [63:0] res;
   input [63:0] l, r;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = subtract(l,r);
endmodule // fp64_sub

module fp64_sub_c (res_r, res_i, l_r, l_i, r_r, r_i); // complex subtraction
   output [63:0] res_r, res_i;
   input [63:0] l_r, l_i, r_r, r_i;
   wire	[63:0]	res_r, res_i;
`include "fphdl64_real_functions_base.inc"
   assign {res_r, res_i} = complex_subtract(l_r, l_i, r_r, r_i);
endmodule // fp64_sub_c

module fp64_mult (res, l, r); // multiplation (l * r)
   output [63:0] res;
   input [63:0] l, r;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = multiply(l,r);
endmodule // fp64_mult

module fp64_mult_c (res_r, res_i, l_r, l_i, r_r, r_i); // complex multiplicaiton
   output [63:0] res_r, res_i;
   input [63:0] l_r, l_i, r_r, r_i;
   wire	[63:0]	res_r, res_i;
`include "fphdl64_real_functions_base.inc"
   assign {res_r, res_i} = complex_multiply(l_r, l_i, r_r, r_i);
endmodule // fp64_mult_c

module fp64_div (res, l, r); // division (l / r)
   output [63:0] res;
   input [63:0] l, r;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = divide(l,r);
endmodule // fp64_div

module fp64_div_c (res_r, res_i, l_r, l_i, r_r, r_i); // complex division
   output [63:0] res_r, res_i;
   input [63:0] l_r, l_i, r_r, r_i;
   wire	[63:0]	res_r, res_i;
`include "fphdl64_real_functions_base.inc"
   assign {res_r, res_i} = complex_divide(l_r, l_i, r_r, r_i);
endmodule // fp64_div_c

module fp64_rem (res, l, r); // remainder
   output [63:0] res;
   input [63:0] l, r;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = remainder(l,r);
endmodule // fp64_rem

module fp64_sqrt (res, arg); // square root
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = square_root(arg);
endmodule // fp64_sqrt

module fp64_log (res, base, arg); // log
   output [63:0] res;
   input  [31:0] base; // integer
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = log(base, arg);
endmodule // fp64_log

module fp64_ln (res, arg); // ln
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = natural_log(arg);
endmodule // fp64_ln

module fp64_pow_fp (res, l, r); // l**r, where l and r are fp64
   output [63:0] res;
   input [63:0] l, r;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = power_of_fp(l,r);
endmodule // fp64_pow_fp

module fp64_pow (res, l, r); // l**r, where l is fp64 and r is integer
   output [63:0] res;
   input  [31:0] r; // integer
   input [63:0]  l;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = power_of(l,r);
endmodule // fp64_pow

module fp64_sin (res, arg); // sin
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = sine(arg);
endmodule // fp64_sin

module fp64_cos (res, arg); // cos
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = cosine(arg);
endmodule // fp64_cos

module fp64_tan (res, arg); // tan
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = tangent(arg);
endmodule // fp64_tan

module fp64_arc_sin (res, arg); // arcsin
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = arc_sine(arg);
endmodule // fp64_arc_sin

module fp64_arc_cos (res, arg); // arccos
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = arc_cosine(arg);
endmodule // fp64_arc_cos

module fp64_arc_tan (res, arg); // arctan
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
   assign res = arc_tangent(arg);
endmodule // fp64_arc_tan

module fp64_equ (res, l, r); // =
   output res;
   input [63:0] l, r;
   wire	res;
`include "fphdl64_real_functions_base.inc"
   assign res = equal(l,r);
endmodule // fp64_equ

module fp64_not_equ (res, l, r); // !=
   output res;
   input [63:0] l, r;
   wire	res;
`include "fphdl64_real_functions_base.inc"
   assign res = not_equal(l,r);
endmodule // fp64_not_equ

module fp64_gteq (res, l, r); // >=
   output res;
   input [63:0] l, r;
   wire	res;
`include "fphdl64_real_functions_base.inc"
   assign res = greater_than_or_equal(l,r);
endmodule // fp64_gteq

module fp64_lteq (res, l, r); // <=
   output res;
   input [63:0] l, r;
   wire	res;
`include "fphdl64_real_functions_base.inc"
   assign res = less_than_or_equal(l,r);
endmodule // fp64_lteq

module fp64_gt (res, l, r); // >
   output res;
   input [63:0] l, r;
   wire	res;
`include "fphdl64_real_functions_base.inc"
   assign res = greater_than(l,r);
endmodule // fp64_gt

module fp64_lt (res, l, r); // <
   output res;
   input [63:0] l, r;
   wire	res;
`include "fphdl64_real_functions_base.inc"
   assign res = less_than(l,r);
endmodule // fp64_lt

module integer_to_fp64 (res, arg); // integer input, fp64 output
   output [63:0] res; // floating point
   input [31:0]  arg; // integer
   wire	[63:0] res;
`include "fphdl64_real_functions_base.inc"
   assign res = integer_to_fp64_func(arg);
endmodule // to_fp64

/*

 module real_to_fp64 (res, arg); // real input, fp64 output
   output [63:0] res; // floating point
   input [63:0]  arg; // Verilog real number
   real_to_fp64_ea u1 ( .res(res), .arg(arg));
 endmodule // to_fp64

use:

assign res = $realtobits(arg);


 from Cadence's Verilog-XL Reference Manual chap. 11 :

"Real Numbers in Port Connections

    The real data type cannot be directly connected to a port. 
    Rather it must be connected indirectly, as shown in the following
    example. The system functions $realtobits and $bitstoreal are 
    used for passing the bit patterns across the module ports.
    
    module driver (net_r); 
       output net_r; 
       real r; 
       wire [64:1] net_r = $realtobits(r); 
    endmodule

    module receiver (net_r); 
       input net_r; 
       wire [64:1] net_r; 
       real r; 
       initial assign r =$bitstoreal(net_r); 
    endmodule 
"

*/

module signed_to_fp64 (res, arg);// signed, parameter: width
   parameter width = 64;
   output [63:0] res; // floating point
   input [width-1:0] arg;
   wire	[63:0] res;
   //  -- NOT Synthisable
   function [63:0] signed_to_fp64_func;
   input signed [width-1:0] arg;
      real real_res;
   begin
      real_res = arg;
      signed_to_fp64_func = $realtobits(real_res);
   end
   endfunction // signed_to_fp64_func
   assign res = signed_to_fp64_func(arg);
endmodule // signed_to_fp64

module unsigned_to_fp64 (res, arg); // unsigned, parameter: width
   parameter width = 64;
   output [63:0] res; // floating point
   input [width-1:0] arg;
   wire	[63:0] res;
   //  -- NOT Synthisable
   function [63:0] unsigned_to_fp64_func;
   input [width-1:0] arg;
      real real_res;
   begin
      real_res = arg;
      unsigned_to_fp64_func = $realtobits(real_res);
   end
   endfunction // unsigned_to_fp64_func
   assign res = unsigned_to_fp64_func(arg);
endmodule // unsigned_to_fp64

module fp64_to_integer (res, arg); // fp64 to integer
   output [31:0] res; // integer
   input [63:0]  arg; // floating point
   wire	[63:0] res;
   integer res_integer;
`include "fphdl64_real_functions_base.inc"
   always @(arg)
	res_integer = fp64_to_integer_func(arg);
   assign res = res_integer;
endmodule // to_integer

module fp64_to_unsigned (res, arg); // fp64 to unsigned, parameter: width
   parameter width = 64;
   output [width-1:0] res; // floating point
   input [63:0] arg;
   wire	[width-1:0] res;
   //  -- NOT Synthisable
   function [width-1:0] fp64_to_unsigned_func;
   input [63:0] arg;
      real real_arg;
      reg  [width-1:0] unsigned_res;
   begin    
      real_arg = $bitstoreal(arg) + 0.5; // rounding here ???
      unsigned_res = real_arg;
      fp64_to_unsigned_func = unsigned_res;
   end
   endfunction // fp64_to_unsigned_func
   assign res = fp64_to_unsigned_func(arg);
endmodule // fp64_to_unsigned

module fp64_to_signed (res, arg); // fp64 to signed, parameter: width
   parameter width = 64;
   output [width-1:0] res; // floating point
   input [63:0] arg;
   wire	[width-1:0] res;
   //  -- NOT Synthisable
   function [width-1:0] fp64_to_signed_func;
   input [63:0] arg;
      real real_arg;
      reg signed [width-1:0] signed_res;
   begin    
      real_arg = $bitstoreal(arg) + 0.5; // rounding here ???
      signed_res = real_arg;
      fp64_to_signed_func = signed_res;
   end
   endfunction // fp64_to_signed_func
   assign res = fp64_to_signed_func(arg);
endmodule // fp64_to_signed

/*

module fp64_to_real (res, arg); // fp64 to real
   output [64:1] res; // Verilog real number
   input [63:0] arg; // floating point
   fp64_to_real_ea u1 ( .res(res), .arg(arg));
endmodule // fp64_to_real

use:

assign res = $bitstoreal(arg);

See real_to_fp64 above

*/

module fp64_Copysign (res, x, y); // copies sign of x to y
   output [63:0] res;
   input [63:0]  x, y;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
//   assign res = fp64_Copysign_func(x,y);
endmodule // fp64_Copysign

module fp64_Scalb (res, y, n); // multiplies y by 2**n (where n is an integer)
   output [63:0] res;
   input [63:0]  y;
   input [31:0]  n; // integer
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
//   assign res = fp64_Scale_by(y,n);
endmodule // fp64_Scalb

module fp64_Logb (res, arg);  // returns the log (base 2) of arg
   output [63:0] res;
   input [63:0]  arg;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
//   assign res = fp64_logb2(arg);
endmodule // fp64_Logb

module fp64_Nextafter (res, x, y); // Gives you the next logical number after x
   output [63:0] res;
   input [63:0]  x, y;
   wire	[63:0]	res;
`include "fphdl64_real_functions_base.inc"
//   assign res = fp64_Nextafter_func(x,y);
endmodule // fp64_Nextafter

module fp64_Finite (res, x); // returns "1" if x is not infinity.
   output res;
   input [63:0]  x;
   wire	res;
`include "fphdl64_real_functions_base.inc"
//   assign res = fp64_Finite_func(x);
endmodule // fp64_Finite

module fp64_Isnan (res, x); // returns "1" is x in any type of NAN
   output res;
   input [63:0]  x;
   wire	res;
`include "fphdl64_real_functions_base.inc"
//   assign res = fp64_Isnan_func(x);
endmodule // fp64_Isnan

module fp64_Unordered (res, x, y); // returns "1" if x or y is a NAN.
   output res;
   input [63:0]  x, y;
   wire	res;
`include "fphdl64_real_functions_base.inc"
//   assign res = fp64_Unordered_func(x,y);
endmodule // fp64_Unordered