Tested with Synopsys 2006.06 sp4, you may be able to use earlier versions, but if you do make sure that you are using the "Presto" compiler.
To load, The easiest way is to add the following lines into your compile script (You need only load the packages you need):
define_design_lib ieee_proposed -path ./ieee_proposed set hdlin_enable_vhdl_floating_point true set hdlin_warn_null_range true analyze -w ieee_proposed -f vhdl standard_additions_c.vhdl analyze -w ieee_proposed -f vhdl std_logic_1164_additions.vhdl analyze -w ieee_proposed -f vhdl numeric_std_additions.vhdl analyze -w ieee_proposed -f vhdl numeric_std_unsigned_c.vhdl analyze -w ieee_proposed -f vhdl math_utility_pkg.vhdl analyze -w ieee_proposed -f vhdl fixed_pkg_c.vhdl analyze -w ieee_proposed -f vhdl float_pkg_c.vhdl # analyze -w work -f vhdl float_synth.vhdl # compile_ultra .. # The following line is needed to remove the negative index that some # downstream tools don't like. change_names -rules verilog -hierarchy
Included in this ZIP file are the following packages (only include the ones you need):
You will also want to look at the Fixed point docuementation and the Floating point docuementation.
I have successfully gotten this packages through both Formality (Synopsys) and Confirmal LEC (Cadence). Drop me an e-mail and I'll show you how.
Notes: