EDPS 2008 Workshop Program:

Speaker

Affiliation

Title/Area of Talk

Thursday, April 17, 2008
08:30 AM - 09:10 AM Welcome, Continental Breakfast

Host: Patrick H. Madden, SUNY Binghamton

Keynote Address - 9:10am - 9:50am

Timothy G. Mattson / Intel

Parallel Computing: Can We Please Do it Right?

 

Session:  Embedded Microprocessor Design

10:00am - 12:30 Session Chair: TBD

 

Grant Martin, Steve Leibson

 Tensilica

Embedded Boot Camp: AMP vs. SMP

Radhika Thekkath MIPS
Max Out Your Multi's
Ian Rickards ARM
Ray Brinks Sonics Inc.
Microprocessor Centric SoC's are Dead
Akash Deshpande ARC
Solutions for SoC Design
Lunch: 12:30 - 1:15
Lunch Discussion: Parallel Computing Bingo

Session:  EDA Standards Panel

1:15 - 2:45pm Session Chair and Organizer: John Darringer (IBM)

John Darringer 

IBM
 

Gary Delp, Technical Director

SPIRIT
 

Jake Buurma and Steve Schulz, President

 SI2
 

Victor Berman, Chairman

 IEEE DASC
 

Rohit Kapur, Chairman

 IEEE TTSC

 Session:  Manufacturing Challenges and Solutions

3pm - 4:15pm Session Organizer: TBD


Puneet Gupta

UCLA/Blaze

Andres Torres

Mentor Graphics

Regular Designs and Computational Lithography: Their Past, Present, and Future

Anantha Sethuraman DFMSim
After the Hype, Are We Ready To Do DFM?

Session: Nuts and Bolts of EDA Tools

4:30pm - 5:45pm Session Chair: TBD

Patrick Groeneveld

Magma

TCL as an EDA tool flow integrator: the good, the bad, and the ugly.


Joao Geada 		CLKda
Efficient Use of Multicore Processors for Timing Analysis

Igor Markov

U Michigan

On Libraries, Reuse, and the Value of EDA Software

EDP Banquet Dinner
Panel Discussion on EDA and the Industry Press
Richard Goering, SCDsource
Gabe Moretti, GabeOnEDA

Friday, April 18, 2008
8:30am-9am Continental Breakfast

Session:  EDA Venture Capital Outlook
9am - 10:30

Juan-Antonio Carballo

Argon VC
Renu Raman Tallwood VC


Semiconductor Trends and Investments

Daya Nadamuni  


The Forecast for EDA

Session:  Power Aware Verfication
10:45-11:30

Bhanu Kapoor, Auturo Salz, Shankar Hemmady

Mimasic/Synopsys

Multi-Voltage Power Managment Verification Issues

Srivasta Vasudevan

Synopsys

Verification Minimization with Karnaugh Maps

Lunch Talk: Aman Joshi, Director of IC Tools, Sun Microsystems

11:45-1pm

Session: Take Me To A Higher Level - Virtualization, ESL, and the Next Generation of EDA Tools
1:15pm - 3pm

Larry Lapides Imperas
Open Virtual Platforms
Michel Genard Virtutech
Virtualized Software Development

Rajesh Gupta

UC San Diego


The Next EDP Challenge: Cost of ASIC Design & Validation

Rishiyur Nikil Bluespec
Using Parallel Atomic Transactions in SoC Design
Alec Stanculescu FinTronic FinSimMath: An Extension of Verilog for Mathematical Descriptions

Closing Remarks

 

Organizing Committee:

General Chair:  Patrick H. Madden

Technical Program Chair:  Gary Smith

Steering Committee Chair: Bhanu Kapoor

Publicity Chair:  Steve Grout

 

Program Committtee:

Michael Bohm (AccelChip)              Aparna Dey (Cadence)                  John Lillis (UIC)

Takahide Inoue (STARC)                  Andrew B. Kahng (UCSD)              José Augusto Lima (U. of Minho)                               

Gabe Moretti (Gabe on EDA)             Naresh Sehgal (Intel)                    Kumar Venkatramani (SoftJin)

Sandeep Shukla (Virginia Tech)     Gary Smith (GarySmithEDA)          Bill Halpin (Synplicity)

Bhanu Kapoor (Mimasic)                  Patrick Madden (Binghamton)      Igor Markov (U. of Michigan)

Elaheh Bozorgzadeh (UCI)                Juan-Antonio Carballo (Argon)    Matt Gutthaus (UCSC)

Steve Grout (Consultant)                 Dwight Hill (Synopsys)                   Patrick Groeneveld (Magma)