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Sessions and papers
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Presenter / moderator
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Files |
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Mon April 26th
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Keynote 1: Integrity Must Be Integral
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Li-Pen Yuan (Synopsys)
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Presentation |
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Session 1: Power-Aware Methodologies
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Gary Smith (Gartner)
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Low-Power Analysis Using Orinoco
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Stan Krolikroski (Chip Vision)
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Paper
Presentation |
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A Policy Based Approach to Low Power Design
Methodology
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Bhanu Kapoor (Atrenta)
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Paper
Presentation |
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PowerTeam: There is more to Verilog beyond
Behavioral Simulation
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Mehmet A Cirit (Library Technologies)
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Paper
Presentation |
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Session 2: Interoperability Advances
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James Hsueh (Synopsys)
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An Industry-led Platform for Interoperability
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Sumit DasGupta (Si2)
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Paper
Presentation |
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Using Tcl to Turn EDA Cousins into Sisters
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Dwight Hill (Synopsys)
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Paper
Presentation |
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Unifying Multiple Tools to Achieve High Performance
SoC Design
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Mark Bales et al. (Reshape)
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Paper
Presentation |
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Session 3: Panel: Applications of interoperable
databases and data models in production flows
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Aparna Dey (Cadence) and Dwight Hill (Synopsys)
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Jim Wilmore (HP)
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Presentation |
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Noel Strader (Synopsys)
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Presentation |
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Scott Peterson (LSI Logic)
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Presentation |
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Dinner Speaker: Architecture and Synthesis
for Power-Efficient FPGAs
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Prof. Jason Cong (UCLA)
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Presentation |
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Tuesday April 27th
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Session 4: Analog/Mixed Signal and SoC Methodologies
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Takahide Inoue (STARC)
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Empowering RISC Processors for Speech Coding:
Algorithms Using a Portable Coprocessor Architecture
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Mehdi Sedighi et al.(Amirkabir University of Technology)
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Missing Analog Tools – A Proposal
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Steve Grout
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Paper
Presentation |
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Impact of Signal Integrity on System-On-Chip
Design Methodologies
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Juan-Antonio Carballo, R. Singh (IBM/VSIA)
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Paper
Presentation |
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Session 5: Advances in Verification and Analysis
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Naresh Sehgal (Intel)
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ARM SoC Verification Matrix Improves HW/SW
Co-Verification
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Jason Andrews (Verisity)
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Paper
Presentation |
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A Methodology to Remove Unwanted Delays in
Outputs and Pre and Post-Synthesis Simulation
Mismatches in Implicit State Machines
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Shahriyar M. Rizvi (AIUB) and Jerry Cupal (U. Wyoming)
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Paper
Presentation |
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HeatGen: A Vectorless Approach to Switching
Activity Generation for IC Power Analysis
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Wolfgang Roethig et al.
(NEC Electronics and V-Cube Technology)
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Paper
Presentation |
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Keynote 2: Trends and Challenges in High-Performance
Microprocessor Design
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Stefan Rusu (Intel)
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Presentation |
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Session 6: Cell-based methodologies
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Juan-Antonio Carballo (IBM)
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Beyond P-Cell and Gate-Level Assumptions:
Accuracy Requirements for Nanometer Design
Simulation
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Brian Marshall (Mentor Graphics)
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Paper
Presentation |
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A Novel EDA flow for SoC Designs based on
Specification Capture, Block-clustering and
Bus-partitioning
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Ashwin K. Kumaraswamy et al. (University
of Edinburgh and Agilent Technologies)
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