Date/time

Sessions and papers

Presenter / moderator

Sun April 13st

7:00 – 9:00 PM

Registration and Reception

Mon April 14^th

8:30 – 8:45 AM

Welcome

General Chair comments

Prog. Chair comments

8:45 – 9:30 AM

Keynote 1
Communications 101 for EDA

Steve Schultz (SI2)

9:45 – 11:45 AM

Impact of design-manufacturing interface (I)

Juan-Antonio Carballo (IBM)

9:45 – 10:15 AM

The X Architecture: Roadmap for Design for Manufacturing Methodology

Ken Rygler (Rygler and Associates)

10:15 – 10:45 AM

Manufacturability Metrics and RET Tradeoffs for Physical Design and Layout

Luigi Capodieci (AMD)

10:45 – 11:15 AM

Design Rules for Real Patterns

Alexander Starikov (Intel)

11:15 – 11:45 PM

Panel

12:00 – 1:00 PM

Lunch

1:00 – 3:30 PM

Impact of design-manufacturing interface (II)

Andrew Kahng (UCSD)

1:00 – 1:30 PM

Layout Methodology Impact of Resolution Enhancement Techniques

Lars Liebmann (IBM)

1:30 – 2:00 PM

Designing-in test & repair IP for manufacturing yield

Yervant Zorian (Virage Logic)

2:00 – 2:30 PM

Impact of DFM and RET on Standard-Cell Design Methodology

Paul de Dood (Prolific)

2:30 – 3:00 PM

The importance of layout density control in semiconductor manufacturing

Vivek Singh (Intel)

3:00 – 3:30 PM

Panel

3:30 – 3:45 PM

Break

3:45 – 6:15 PM

Unified databases and data models

Gary Smith (Gartner)

3:45 – 4:15 PM

Design Systems Evolution and the Need for a Standard Data Model

John Darringer (IBM)

4:15 – 4:45 PM

Facilitating EDA Flow Interoperability with the OpenAccess Design Database

Mark Bales (Cadence)

4:45 – 5:15 PM

Introduction to Milkyway

Lawrence Brevard (Synopsys)

5:15 –5:45 PM

Interoperability, Data Models, and Databases

Michael Riepe (Magma)

5:45 –6:15 PM

Panel

6:30 – 8:00 PM

Dinner

Tuesday April 15^th

7:30 – 8:15 AM

Continental Breakfast

8:15 – 10:00 AM

New automated methodologies and flows (I)

Naresh Sehgal (Intel)

8:15 – 8:45 AM

Hard IP Group Design

Howard Sachs (Telairity)

8:45 – 9:15 AM

The Arrow of Time:

Following Timing Constraints in an RTL to GDSII Flow

Dwight Hill (Synopsys)

9:15 – 9:45 AM

eL-Architect: Using a Design Flow e-Learning tool in CAD/EDA and VLSI education

José A. Lima (Univ. of Minho)

9:45 – 10:00 PM

Panel + Break

10:00AM – 12:00PM

New automated methodologies and flows (II)

Takahide Inoue (STARC)

10:00 – 10:30 AM

Software-Compiled System Design: A Methodology for Field-Programmable Design

Jeff Jussel (Celoxica)

10:30 – 11:00 PM

Improving SoC Design Flows with Robust and Precise Embedded Memory Models

Jay Abraham (Silicon Metrics)

11:00 – 11:30 PM

Building Design Process in a Startup Company

David Gates (ATI)

11:30 – 12:00 PM

Panel + break

12:00 – 1:00 PM

Lunch

1:00 – 1:30 PM

Keynote 2
Design Challenges & Solutions for 90nm/130nm Technology

David Lan (TSMC)

1:30 – 4:00 PM

Methodologies of Industrial Usage of Formal Verification

Sandeep Shukla (Virginia Tech)

1:30 – 2:00 PM

Property Specification: The key to an Assertion-Based Verification Platform

Harry Foster (Verplex Systems)

2:00 – 2:30 PM

A Verification Synergy: Constraint-Based Verification

Carl Pixley (Synopsys)

2:30 – 3:00 PM

Formal Interface Compliance Verification

C. Norris Ip (Tempus Fugit)

3:00 – 3:30 PM

Experience with Applying Formal Methods to Protocol Specification and System Arch

Ching-Tsun Chou (Intel)

3:30 – 4:00 PM

Panel

4:00 – 4:15 PM

Adjourn

Papers in EDP package but not to be presented

PROGRESS: Combining Topdown and Bottom-up System Design Methodology

James Armstrong et al. (Virginia Tech.)

Total Hot Spot Management from Design Rule Definition to Silicon Fabrication

Soichi Inoue (Toshiba)

Code Generation from a Single Source Structural Specification

C. Schneider (Micronas)