Sponsored by

In cooperation with ACM/SIGDA


With generous corporate support from
IBM Microelectronics
Magma Design Automation
Simplex Solutions

CALL FOR PAPERS - EDP 2001

ELECTRONIC DESIGN PROCESSES 2001
APRIL 9-10, 2001
MONTEREY BEACH HOTEL
MONTEREY, CALIFORNIA
http://www.eda.org/edps/edp01


CALL FOR PAPERS (PDF version)

The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. As the requirements and complexities of electronic design increase, past ad hoc approaches to design processes are proving inadequate. The workshop focuses on the facilitation and improvement of the overall design process, rather than on the functions of the individual tools themselves. The core audience for EDP-2001 consists of CAD system integrators and methodologists, along with academic researchers and design team managers.
Focus in 2001: It's the Methodology, Stupid!

The focus of the EDP-2001 Workshop will be Methodology. We are soliciting submissions which shed light on the real methodologies used for today's chip designs -- covering issues ranging from formats and scripting languages to RTL-down timing closure to integration of RF/analog on complex SOCs. Aspects of methodology which are of interest include but are not limited to:
  • Methodology best practices and experiences
  • Metrics for methodologies
    • Effort/cost, turn-around time, productivity
  • Methodology scaling and migration
    • Ramping up from pipecleaner test cases to diskbuster real designs
    • Evolution of a methodology for new technologies
  • Human issues
    • Methodologies for large/distributed design teams
    • Training and education
  • Futures
    • Future methodology needs and concepts
    • Process technology and level of integration
    • Tool/algorithm technologies
    • Interoperability and ongoing interoperability initiatives
    • Impact of the web and new computation platforms or tool licensing models
Methodology domains of particular interest are:
  • Functional verification
  • RTL-to-GDSII design closure
  • HW/SW co-design
  • IP reuse
Driving technologies and applications of particular interest are:
  • SOC
  • Analog/mixed signal
  • RF
  • MEMS

PAPER SUBMISSION

IMPORTANT DATES

Submission deadline February 9, 2001
Acceptance notification February 23, 2001
Camera-ready copy due April 2, 2001
Workshop start April 8, 2001

ORGANIZING COMMITTEE

Steering Committee Steve Grout (Tality)
David Hathaway (IBM)
Dwight Hill (Synopsys)
José Augusto D. F. Lima (Univ. of Minho)
Margarida Jacome (UT-Austin)
Andrew B. Kahng (UCSD)
Naresh Sehgal (Intel)
General Chair David Hathaway, IBM
Technical Program Chair Andrew B. Kahng, UCSD
Publicity Chair Stefanus Mantik, UCLA
Local Arrangements Chair Rik Vigeland, Mentor