Electronic Design Process Subcommittee of IEEE DATC

Online Record of the
EDP 2006 Workshop

Prior Years: 2005 2004 2003 2002 2001 2000

Held
April 13 and 14, 2005, in Monterey California

 

Organized in cooperation with ISPD ( www.ispd.cc )

This "archival" site was created May 10th, to record events from EDPS 2006.

Opening Session Steve Longoria (IBM) and John LIllis (UIC and EDP06 Chair)

Welcome
John Lillis (UIC)
EDP06 Workshop
General Chair

John Lillis Workshop General Chair

Opening Keynote
Steve Longoria (IBM)
Design in the New Open Semiconductor Platform
BIO

Steve Longoria (IBM) - Opening Keynoter

Session:
Above RTL I
Jason Cong (UCLA)
"Platform Based Behavioral and System Synthesis"
PDF

Rishiyur Nikhil (Bluespec)
"Eliminating Verification using Automated Formal Interface Contracts"
Presentation
Winser Alexander (NCSU), Ramsey Hourani, Ravi Jenkal, and Rhett Davis
Tool Integration for Signal Processing Architectural Exploration"
PDF
Session
Issues Related to Manufacturing
Session Chair:
Nishath Verghese (Clearshape) 		a3
Lou Scheffer (Cadence)
"Recommended Rules NOT Recommended"
Abstract
Presentation
Luigi Capodieci (AMD)
"Layout Printability Verification and Physical Design Regularity: Roadmap Enablers for the Next Decade"
Abstract
Presentation
Andrew B. Kahng (UCSD)
Title TBA
Session:  
Database Issues in Design Processes
Session Chair:
Patrick Groeneveld (Magma) 		a4
Christoph Albrecht (Cadence Berkeley Labs)
OAGear: OpenAccess for Academic Research
PDF
pdf
Mark Bales (Synopsys)
"Using Open Access to Replace a Proprietary EDA Database"
Presentation PPT
Session
Interconnect and Physical Issues in Design 		a6
Chung-Kuan Cheng (UCSD)
"Revamping the Electronic Design Process to Embrace Interconnect Dominance"
PDF
Valavan Manohararajah (Altera)
"Physical Synthesis Challenges for Programmable Logic"
Abstract
Presentation PDF
Tarneh Taghavi, Majid Sarafzadeh (UCLA)
"Blockage Oriented Placement"
Abstract
PDF
Matthew C Bell (SCU) Patrick Madden (Binghamton)"
Fundamental Limits of Circuit Placement"
PDF 		a5  
Bao Liu (UCSD)
"Stochastic Power/Ground Supply Voltage Analysis via Moment and Correlation Computation by Statistical Transient Toggling Analysis"
Abstract
PDF
Keynote:
Kurt Keutzer (UC Berkeley)
"Will the Real ESL Please Stand Up"
TBD  		a9
Session:
Design Above RTL II  		a10
Carlo Brandolese, Fabio Salice, Laura Frigerio, Cristiana Bolchini (Politecnio Di Milano)
"Data-path Oriented, IP-Based Framework for Flexible Design Exploration"
Abstract
PDF
Michael Bohm (Xilinx)
"High-Level Specification and Design of DSP Systems"
Abstract
PDF   		a2
Rajesh Gupta (UCSD)
"ESL: Discovering Method in Designer Madness"
TBD
Keynote:
Milind Karnik (Intel)
 "Rising Cost of Platform Validation"
a11
Session:
Emerging Issues in EDA 		  a12
Juan-Antonio Carballo (IBM)
"The Venture Capital Environment and its Implications for EDA"
TBD
Naresh Sehgal (Intel)
"New Usage Models With Virtualization"
PDF
Ralph Marlett (Atrenta)
"Facilitating At-Speed Test at the Register Transfer Level"
BIO
BIO
Abstract
Keynote:
Jan Rabaey (UC Berkeley), 
"Design at the End of the Roadmap"
TBD  		a14
Session:
Parallelism in System Design 		a15
Daya Nadamuni (Gartner/Dataquest):
"MultiCore Design Needs: A System Level View"
Abstract
PDF
Sven Brehmer (Polycore Software)
"Enabling Communications by Enhancing the Multicore Ecosystem"
Abstract
PDF
Session:
Design Above RTL III 
Session Chair:
Steve Leibson (Tensilica) 		a16
Gary Smith (Gartner/Dataquest):
"In Search of an ESL Methodology"
ppt
Presentation   		a8
Francesco Regazzoni (ALaRI – University of Lugano):
"Hardware/Software Partitioning for Operating Systems: A Behavioral Synthesis Approach"
PDF
Nikil Dutt (UCI):
"Exploring SoC Communication Architectures for Performance and Power"
Abstract



The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. As the requirements and complexities of electronic design increase, past ad hoc approaches to design processes are proving inadequate. The workshop focuses on the facilitation and improvement of the overall design process, rather than on the functions of the individual tools themselves. Topics include interactions among and between tools and designers, the infrastructures supporting these interactions, and the frameworks in which these interactions take place.

General Information on EDPS:

The Electronic Design Process Subcommittee (EDPS) is a technical subcommittee of the IEEE Computer Society's Design Automation Technical Committee (DATC).

Objectives of the EDPS:

The EDPS focuses on design process for electronics products with respect to design, design technology, and design productivity for both today's and coming technologies.

Activities and Achievements:

To provide a forum for electronics designers and CAD/EDA technologists to work together on design process issues, the EDPS holds an annual workshop to discuss design and EDA process problems, plans, and research.

In addition, the EDPS often holds a Birds of a Feather (BOF) at annual Design Automation Conferences (DAC), and also meets at ICCAD.  Contact the EDPS Steering Committee for details.

Electronic Design Process Email List:


The email list for general information and announcements on EDPS is edps-all@verilog.org.
To join the email list for the IEEE DATC EDPS group, send a request to the sysop below.

 

EDPS Co-chairs:
Dwight Hill and Naresh Sehgal

www.eda-stds.org/edps Group Sysop:
Steve Grout

About the eda-stds.org machine

There are many groups with repositories and email exploders on the VHDL International Users' Forum (VIUF) Internet Services (VIIS) System. For more information about the VIIS supported features and access mechanisms (such as email, Internet or public dial-up), click here.

Last updated June 16, 2006, by Steve Grout - EDPS Webmaster