-- --------------------------------------------------------------------------- -- -- ASSERT_ALWAYS -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_ALWAYS - An invariant concurrent assertion to ensure -- that its argument always evaluates TRUE -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_always IS GENERIC (severity_level: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT ALWAYS VIOLATION"); PORT (clk, reset_n, test_expr: IN std_ulogic); END assert_always; ARCHITECTURE ovl OF assert_always IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; ELSE IF (test_expr = '0') THEN valid <= '0'; ELSE valid <= '1'; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_CHANGE -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_CHANGE - Clock bounded window expecting a change -- -- --------------------------------------------------------------------------- -- } */- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_change IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; num_cks: INTEGER := 1; flag: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT CHANGE VIOLATION"); PORT (clk, reset_n: IN std_ulogic; start_event: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_change; ARCHITECTURE ovl OF assert_change IS TYPE stateT IS (CHANGE_START, CHANGE_CHECK); CONSTANT FLAG_IGNORE_NEW_START: INTEGER := 0; CONSTANT FLAG_RESET_ON_START : INTEGER := 1; CONSTANT FLAG_ERR_ON_START : INTEGER := 2; -- SIGNAL valid: std_ulogic := '1'; SIGNAL flag_error: std_ulogic := '0'; SIGNAL flag_para_error: std_ulogic := '0'; SIGNAL rst_n: std_ulogic; SIGNAL ii: INTEGER; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); ASSERT flag_error = '0' REPORT msg & " : illegal start event" SEVERITY ovlSevTab(severity_level); ASSERT flag_para_error = '0' REPORT msg & " : illegal flag parameter" SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := CHANGE_START; VARIABLE r_change: std_ulogic := '0'; VARIABLE r_test_expr : UNSIGNED((width-1) DOWNTO 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN r_state := CHANGE_START; r_change := '0'; valid <= '1'; flag_error <= '0'; flag_para_error <= '0'; r_test_expr := test_expr; ELSE CASE (r_state) IS WHEN CHANGE_START => IF (start_event = '1') THEN r_change := '0'; r_state := CHANGE_CHECK; r_test_expr := test_expr; ii <= num_cks; END IF; WHEN CHANGE_CHECK => -- Count clock ticks IF (start_event = '1') THEN CASE (flag) IS WHEN FLAG_IGNORE_NEW_START => IF (ii > 0) THEN ii <= ii-1; END IF ; WHEN FLAG_RESET_ON_START => ii <= num_cks; WHEN FLAG_ERR_ON_START => flag_error <= '1'; WHEN OTHERS => flag_para_error <= '1'; END CASE; ELSIF (ii > 0) THEN ii <= ii-1; END IF; -- // Check that the property is true IF (r_test_expr /= test_expr) THEN r_change := '1'; END IF; -- -- go to start state on last check IF ((ii = 1) AND NOT((start_event = '1') AND (flag = FLAG_RESET_ON_START))) THEN r_state := CHANGE_START; -- Check that the property is true IF ((r_change = '0') AND (r_test_expr = test_expr)) THEN valid <= '0'; END IF; END IF; -- r_test_expr := test_expr; END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_DECREMENT -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_DECREMENT - An invariant concurrent assertion to ensure -- that an expression (or variable) decreases by -- exactly a defined value (default 1). -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_decrement IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; value: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT DECREMENT VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_decrement; ARCHITECTURE ovl OF assert_decrement IS SIGNAL valid: std_ulogic := '1'; SIGNAL r_reset_n: std_ulogic := '0'; SIGNAL r_r_reset_n: std_ulogic := '0'; SIGNAL last_test_expr: UNSIGNED((width-1) DOWNTO 0); SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE temp_expr : UNSIGNED(width downto 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; r_reset_n <= '0'; r_r_reset_n <= '0'; ELSE r_reset_n <= '1'; r_r_reset_n <= r_reset_n; last_test_expr <= test_expr; -- check second clock after reset IF (((r_reset_n='1') AND (r_r_reset_n='1')) AND (last_test_expr /= test_expr)) THEN temp_expr := ('0' & last_test_expr) - ('0' & test_expr); IF (UNSIGNED(temp_expr(width-1 downto 0)) /= value) THEN valid <= '0'; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_DELTA -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_DELTA - An invariant concurrent assertion to ensure -- that an expression (or variable) will only -- change values by at least MIN and at most MAX. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_delta IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; min: INTEGER := 1; max: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT DELTA VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_delta; ARCHITECTURE ovl OF assert_delta IS SIGNAL valid: std_ulogic := '1'; SIGNAL r_reset_n: std_ulogic := '0'; SIGNAL r_r_reset_n: std_ulogic := '0'; SIGNAL last_test_expr: UNSIGNED((width-1) DOWNTO 0); SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE temp_expr1 : UNSIGNED(width downto 0); VARIABLE temp_expr2 : UNSIGNED(width downto 0); VARIABLE int_temp1 : INTEGER; VARIABLE int_temp2 : INTEGER; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; r_reset_n <= '0'; r_r_reset_n <= '0'; ELSE r_reset_n <= '1'; r_r_reset_n <= r_reset_n; last_test_expr <= test_expr; -- check second clock afer reset IF (((r_reset_n='1') AND (r_r_reset_n='1')) AND (last_test_expr /= test_expr)) THEN temp_expr1 := ('0' & last_test_expr) - ('0' & test_expr); temp_expr2 := ('0' & test_expr) - ('0' & last_test_expr); int_temp1 := CONV_INTEGER(temp_expr1(width-1 downto 0)); int_temp2 := CONV_INTEGER(temp_expr2(width-1 downto 0)); IF (NOT(((int_temp1>=min) AND (int_temp1<=max)) OR ((int_temp2>=min) AND (int_temp2<=max)))) THEN ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); valid <= '0'; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_EVEN_PARITY -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_EVEN_PARITY - An invariant concurrent assertion to -- ensure that its argument has an even number of std_ulogics asserted -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_even_parity IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT EVEN PARITY VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_even_parity; ARCHITECTURE ovl OF assert_even_parity IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; ELSE valid <= not (xorr(test_expr)); END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_HANDSHAKE -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_HANDSHAKE - Validate proper handshaking behavior of -- req / ack type of signals -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_handshake IS GENERIC (severity_level: INTEGER := 0; min_ack_cycle: INTEGER := 0; max_ack_cycle: INTEGER := 0; req_drop: INTEGER := 0; deassert_count: INTEGER := 0; max_ack_length: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT HANDSHAKE VIOLATION"); PORT (clk, reset_n: IN std_ulogic; req, ack: IN std_ulogic); END assert_handshake; -- // synopsys template -- // ovl assertion_library ARCHITECTURE ovl OF assert_handshake IS TYPE stateT IS (REQ_ACK_START, REQ_ACK_WAIT, REQ_ACK_ERR, REQ_ACK_DEASSERT); -- SIGNAL error_max_ack_length: std_ulogic := '0'; SIGNAL error_multiple_req: std_ulogic := '0'; SIGNAL error_min_ack_cycle: std_ulogic := '0'; SIGNAL error_max_ack_cycle: std_ulogic := '0'; SIGNAL error_ack_without_req: std_ulogic := '0'; SIGNAL error_req_drop: std_ulogic := '0'; SIGNAL error_req_deassert: std_ulogic := '0'; SIGNAL rst_n: std_ulogic; SIGNAL ii, jj: INTEGER := 0; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT (error_max_ack_length = '0') REPORT msg & " : ack max length violation" SEVERITY ovlSevTab(severity_level); ASSERT (error_multiple_req = '0') REPORT msg & " : multiple req violation" SEVERITY ovlSevTab(severity_level); ASSERT (error_min_ack_cycle = '0') REPORT msg & " : ack min cycle violation" SEVERITY ovlSevTab(severity_level); ASSERT (error_max_ack_cycle = '0') REPORT msg & " : ack max cycle violation" SEVERITY ovlSevTab(severity_level); ASSERT (error_ack_without_req = '0') REPORT msg & " : ack without req violation" SEVERITY ovlSevTab(severity_level); ASSERT (error_req_drop = '0') REPORT msg & " : req drop violation" SEVERITY ovlSevTab(severity_level); ASSERT (error_req_deassert = '0') REPORT msg & " : req deassert violation" SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state: stateT := REQ_ACK_START; VARIABLE r_req: std_ulogic := '0'; VARIABLE r_ack: std_ulogic := '0'; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; IF (rst_n = '0') THEN r_state := REQ_ACK_START; r_ack := '0'; r_req := '0'; -- ii <= 0; jj <= 0; -- error_max_ack_length <= '0'; error_multiple_req <= '0'; error_min_ack_cycle <= '0'; error_max_ack_cycle <= '0'; error_ack_without_req <= '0'; error_req_drop <= '0'; error_req_deassert <= '0'; ELSE CASE (r_state) IS WHEN REQ_ACK_START => IF ((max_ack_length /= 0) AND (ack = '1') AND (r_ack = '1')) THEN jj <= jj+1; IF (jj >= max_ack_length) THEN r_state := REQ_ACK_ERR; error_max_ack_length <= '1'; END IF; END IF; IF (req = '1') THEN IF ((r_ack = '1') AND (ack = '1') AND (r_req = '0')) THEN r_state := REQ_ACK_ERR; error_multiple_req <= '1'; ELSIF ((deassert_count /= 0) AND (r_req = '1') AND (req = '1') AND (ack = '0')) THEN r_state := REQ_ACK_DEASSERT; ii <= deassert_count; ELSIF ((min_ack_cycle /= 0) AND (ack = '1') AND (r_ack = '0')) THEN error_min_ack_cycle <= '1'; ELSIF (ack = '0') THEN r_state := REQ_ACK_WAIT; ii <= 1; jj <= 0; END IF; ELSIF ((ack = '1') AND (r_ack = '0')) THEN r_state := REQ_ACK_ERR; error_ack_without_req <= '1'; END IF; WHEN REQ_ACK_WAIT => ii <= ii + 1; IF (ack = '1') THEN r_state := REQ_ACK_START; jj <= 1; END IF; -- IF ((min_ack_cycle /= 0) AND (ii < min_ack_cycle) AND (ack = '1')) THEN r_state := REQ_ACK_ERR; error_min_ack_cycle <= '1'; ELSIF ((max_ack_cycle /= 0) AND (ii >= max_ack_cycle)) THEN r_state := REQ_ACK_ERR; error_max_ack_cycle <= '1'; ELSIF ((req_drop = 1) AND (req = '0')) THEN r_state := REQ_ACK_ERR; error_req_drop <= '1'; ELSIF ((req = '1') AND (r_req = '0')) THEN r_state := REQ_ACK_ERR; error_multiple_req <= '1'; END IF; WHEN REQ_ACK_ERR => IF ((req = '1') AND (ack = '0') AND (r_req = '0')) THEN r_state := REQ_ACK_WAIT; ii <= 0; jj <= 0; ELSIF ((ack = '0') AND (r_ack = '1')) THEN r_state := REQ_ACK_START; ii <= 0; jj <= 0; END IF; WHEN REQ_ACK_DEASSERT => ii <= ii-1; IF (ii = 1) THEN IF (req = '1') THEN r_state := REQ_ACK_ERR; error_req_deassert <= '1'; ELSE r_state := REQ_ACK_START; END IF; END IF; END CASE; r_ack := ack; r_req := req; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_INCREMENT -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_INCREMENT - An invariant concurrent assertion to ensure -- that an expression (or variable) will only -- increase by MAX. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_increment IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; value: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT INCREMENT VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_increment; ARCHITECTURE ovl OF assert_increment IS SIGNAL valid: std_ulogic := '1'; SIGNAL r_reset_n: std_ulogic := '0'; SIGNAL r_r_reset_n: std_ulogic := '0'; SIGNAL last_test_expr: UNSIGNED((width-1) DOWNTO 0); SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE temp_expr : UNSIGNED(width downto 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; r_reset_n <= '0'; r_r_reset_n <= '0'; ELSE r_reset_n <= '1'; r_r_reset_n <= r_reset_n; last_test_expr <= test_expr; -- check second clock afer reset IF (((r_reset_n AND r_r_reset_n) = '1') AND (last_test_expr /= test_expr)) THEN temp_expr := ('0' & test_expr) - ('0' & last_test_expr); IF (UNSIGNED(temp_expr(width-1 downto 0)) /= value) THEN valid <= '0'; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_NEVER -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_NEVER - An invariant concurrent assertion to ensure -- that its argument never evaluates TRUE -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_never IS GENERIC (severity_level: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT NEVER VIOLATION"); PORT (clk, reset_n, test_expr: IN std_ulogic); END assert_never; ARCHITECTURE ovl OF assert_never IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; ELSE IF (test_expr = '1') THEN valid <= '0'; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_NO_OVERFLOW -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_NO_OVERFLOW - An invariant concurrent assertion to ensure -- that an expression (or variable) does not -- change from a MAX value to a value <= MIN limit. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; use std.textio.all; use ieee.std_logic_textio.all; ENTITY assert_no_overflow IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; min: INTEGER := 0; max: INTEGER := -1; options: INTEGER := 0; msg: STRING := "ASSERT NO OVERFLOW VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_no_overflow; ARCHITECTURE ovl OF assert_no_overflow IS TYPE stateT IS (OVERFLOW_START, OVERFLOW_CHECK); SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; SIGNAL pmax : INTEGER; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- pmax <= max when (max > 0) else (2**width -1); rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := OVERFLOW_START; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN r_state := OVERFLOW_START; ELSE IF (r_state = OVERFLOW_START) THEN IF (test_expr = pmax) THEN r_state := OVERFLOW_CHECK; END IF; ELSIF (r_state = OVERFLOW_CHECK) THEN IF (test_expr /= pmax) THEN r_state := OVERFLOW_START; IF ((test_expr <= min) OR (test_expr > pmax)) THEN valid <= '0'; END IF; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_NO_TRANSITION -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_NO_TRANSITION - Check for illegal state transition. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_no_transition IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT NO TRANSITION VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0); start_state: IN UNSIGNED((width-1) DOWNTO 0); next_state: IN UNSIGNED((width-1) DOWNTO 0)); END assert_no_transition; ARCHITECTURE ovl OF assert_no_transition IS --TYPE stateT IS (NO_TRANSITION_START, NO_TRANSITION_CHECK); TYPE stateT IS (INIT_STATE, CHECK_STATE); -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE assert_state : stateT := INIT_STATE; VARIABLE r_test_expr : UNSIGNED((width-1) DOWNTO 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN assert_state := INIT_STATE; valid <= '1'; r_test_expr := test_expr; ELSE CASE (assert_state) IS WHEN INIT_STATE => IF (test_expr = start_state) THEN assert_state := CHECK_STATE; r_test_expr := test_expr; END IF; WHEN CHECK_STATE => -- Count clock ticks IF (r_test_expr /= test_expr) THEN assert_state := INIT_STATE; -- Check that the property is true IF (test_expr = next_state) THEN valid <= '0'; END IF; END IF; r_test_expr := test_expr; END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_NO_UNDERFLOW -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_NO_UNDERFLOW - An invariant concurrent assertion to ensure -- that an expression (or variable) does not -- change from a MIN limit value to a MAX value. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_no_underflow IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; min: INTEGER := 0; max: INTEGER := -1; options: INTEGER := 0; msg: STRING := "ASSERT NO UNDERFLOW VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_no_underflow; ARCHITECTURE ovl OF assert_no_underflow IS TYPE stateT IS (UNDERFLOW_START, UNDERFLOW_CHECK); SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; SIGNAL pmax : INTEGER; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); pmax <= max when (max > 0) else (2**width -1); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := UNDERFLOW_START; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN r_state := UNDERFLOW_START; valid <= '1'; ELSE IF (r_state = UNDERFLOW_START) THEN IF (test_expr = min) THEN r_state := UNDERFLOW_CHECK; END IF; ELSIF (r_state = UNDERFLOW_CHECK) THEN IF (test_expr /= min) THEN r_state := UNDERFLOW_START; IF ((test_expr >= pmax) OR (test_expr < min)) THEN valid <= '0'; END IF; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_ODD_PARITY -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_ODD_PARITY - An invariant concurrent assertion to -- ensure that its argument has an odd number of std_ulogics asserted -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_odd_parity IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT ODD PARITY VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_odd_parity; ARCHITECTURE ovl OF assert_odd_parity IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; ELSE valid <= xorr(test_expr); END IF; END PROCESS; -- synopsys translate_on END ovl; -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_ONE_HOT -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_ONE_HOT - An invariant concurrent assertion to ensure -- that only one std_ulogic of a variable is active high. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_one_hot IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 32; options: INTEGER := 0; msg: STRING := "ASSERT ONE HOT VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_one_hot; ARCHITECTURE ovl OF assert_one_hot IS CONSTANT ZERO : UNSIGNED((width-1) DOWNTO 0) := (OTHERS => '0'); -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; ELSIF (test_expr = ZERO) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); ELSIF (((+test_expr) AND (test_expr - 1)) /= std_logic_vector(ZERO)) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); ELSE valid <= '1'; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_PROPOSITION -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_PROPOSITION - An invariant concurrent assertion to ensure -- that its argument always evaluates TRUE at -- all times. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_proposition IS GENERIC (severity_level: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT PROPOSITION VIOLATION"); PORT (reset_n, test_expr: IN std_ulogic); END assert_proposition; ARCHITECTURE ovl OF assert_proposition IS SIGNAL proposition: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT proposition = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS (test_expr) BEGIN IF (rst_n = '0') THEN proposition <= '1'; ELSIF (test_expr = '1') THEN proposition <= '1'; ELSE proposition <= '0'; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_PROP_ONE_HOT -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_PROP_ONE_HOT - An invariant concurrent assertion to ensure -- that its argument always evaluates TRUE at -- all times. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_prop_one_hot IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 32; inactive: INTEGER := 2; options: INTEGER := 0; msg: STRING := "ASSERT PROPOSITIONAL ONE HOT VIOLATION"); PORT (reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_prop_one_hot; ARCHITECTURE ovl OF assert_prop_one_hot IS SIGNAL prop_one_hot: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT prop_one_hot = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS (test_expr) VARIABLE count: INTEGER RANGE 0 TO width; BEGIN IF (rst_n = '0') THEN prop_one_hot <= '1'; ELSE count := 0; FOR i IN 0 TO (width-1) LOOP IF (test_expr(i) /= '0') THEN count := count + 1; END IF; END LOOP; IF (count = 1) THEN prop_one_hot <= '1'; ELSE prop_one_hot <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_PROP_ONE_COLD -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_PROP_ONE_COLD - An invariant concurrent assertion to ensure -- that its argument always evaluates TRUE at -- all times. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_prop_one_cold IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 32; inactive: INTEGER := 2; options: INTEGER := 0; msg: STRING := "ASSERT PROPOSITIONAL ONE COLD VIOLATION"); PORT (reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_prop_one_cold; ARCHITECTURE ovl OF assert_prop_one_cold IS SIGNAL prop_one_cold: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT prop_one_cold = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS (test_expr) VARIABLE count: INTEGER RANGE 0 TO width; BEGIN IF (rst_n = '0') THEN prop_one_cold <= '1'; ELSE count := 0; FOR i IN 0 TO (width-1) LOOP IF (test_expr(i) /= '1') THEN count := count + 1; END IF; END LOOP; IF (count = 1) THEN prop_one_cold <= '1'; ELSE prop_one_cold <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_PROP_ONE_ONE_COLD -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_PROP_ONE_ONE_COLD - An invariant concurrent assertion to ensure -- that its argument always evaluates TRUE at -- all times. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_prop_one_one_cold IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 32; inactive: INTEGER := 2; options: INTEGER := 0; msg: STRING := "ASSERT PROPOSITIONAL ONE ONE COLD VIOLATION"); PORT (reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_prop_one_one_cold; ARCHITECTURE ovl OF assert_prop_one_one_cold IS SIGNAL prop_one_one_cold: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT prop_one_one_cold = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS (test_expr) VARIABLE count: INTEGER RANGE 0 TO width; BEGIN IF (rst_n = '0') THEN prop_one_one_cold <= '1'; ELSE count := 0; FOR i IN 0 TO (width-1) LOOP IF (test_expr(i) /= '1') THEN count := count + 1; END IF; END LOOP; IF (count <= 1) THEN prop_one_one_cold <= '1'; ELSE prop_one_one_cold <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_PROP_ZERO_ONE_HOT -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_PROP_ZERO_ONE_HOT - An invariant concurrent assertion to ensure -- that its argument always evaluates TRUE at -- all times. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_prop_zero_one_hot IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 32; options: INTEGER := 0; msg: STRING := "ASSERT PROPOSITIONAL ZERO ONE HOT VIOLATION"); PORT (reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_prop_zero_one_hot; ARCHITECTURE ovl OF assert_prop_zero_one_hot IS SIGNAL prop_zero_one_hot: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT prop_zero_one_hot = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS (test_expr) VARIABLE count: INTEGER RANGE 0 TO width; BEGIN IF (rst_n = '0') THEN prop_zero_one_hot <= '1'; ELSE count := 0; FOR i IN 0 TO (width-1) LOOP IF (test_expr(i) /= '0') THEN count := count + 1; END IF; END LOOP; IF (count <= 1) THEN prop_zero_one_hot <= '1'; ELSE prop_zero_one_hot <= '0'; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_RANGE -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_RANGE - An invariant concurrent assertion to ensure -- that an expression (or variable) is bounded -- within a valid range. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_range IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; min: INTEGER := 1; max: INTEGER := -1; options: INTEGER := 0; msg: STRING := "ASSERT RANGE VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_range; ARCHITECTURE ovl OF assert_range IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; SIGNAL pmax : INTEGER; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- pmax <= max when (max > 0) else (2**width -1); rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; ELSE IF (test_expr < min) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); ELSIF (test_expr > pmax) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); ELSE valid <= '1'; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- } */ -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_TIME -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_TIME - An invariant concurrent assertion to ensure -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_time IS GENERIC (severity_level: INTEGER := 0; num_cks: INTEGER := 1; flag: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT TIME VIOLATION"); PORT (clk, reset_n: IN std_ulogic; start_event: IN std_ulogic; test_expr: IN std_ulogic); END assert_time; ARCHITECTURE ovl OF assert_time IS TYPE stateT IS (TIME_START, TIME_CHECK); CONSTANT FLAG_IGNORE_NEW_START: INTEGER := 0; CONSTANT FLAG_RESET_ON_START : INTEGER := 1; CONSTANT FLAG_ERR_ON_START : INTEGER := 2; -- SIGNAL valid: std_ulogic := '1'; SIGNAL flag_error: std_ulogic := '0'; SIGNAL flag_para_error: std_ulogic := '0'; SIGNAL rst_n: std_ulogic; SIGNAL ii: INTEGER; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); ASSERT flag_error = '0' REPORT msg & " : illegal start event" SEVERITY ovlSevTab(severity_level); ASSERT flag_para_error = '0' REPORT msg & " : illegal flag parameter" SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := TIME_START; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN r_state := TIME_START; valid <= '1'; flag_error <= '0'; flag_para_error <= '0'; ELSE CASE (r_state) IS WHEN TIME_START => IF (start_event = '1') THEN r_state := TIME_CHECK; ii <= num_cks; END IF; WHEN TIME_CHECK => -- Count clock ticks IF (start_event = '1') THEN CASE (flag) IS WHEN FLAG_IGNORE_NEW_START => IF (ii > 0) THEN ii <= ii-1; END IF ; WHEN FLAG_RESET_ON_START => ii <= num_cks; WHEN FLAG_ERR_ON_START => flag_error <= '1'; WHEN OTHERS => flag_para_error <= '1'; END CASE; ELSIF (ii > 0) THEN ii <= ii-1; END IF; -- // Check that the property is true IF (test_expr /= '1') THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; -- -- go to start state on last check IF ((ii = 1) AND NOT((start_event = '1') AND (flag = FLAG_RESET_ON_START))) THEN r_state := TIME_START; END IF; -- END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_TRANSITION -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_TRANSITION - Validate legal state transition. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_transition IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT TRANSITION VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0); start_state: IN UNSIGNED((width-1) DOWNTO 0); next_state: IN UNSIGNED((width-1) DOWNTO 0)); END assert_transition; ARCHITECTURE ovl OF assert_transition IS --TYPE stateT IS (TRANSITION_START, TRANSITION_CHECK); TYPE stateT IS (INIT_STATE, CHECK_STATE); -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE assert_state : stateT := INIT_STATE; VARIABLE r_next_state : UNSIGNED((width-1) DOWNTO 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN assert_state := INIT_STATE; r_next_state := test_expr; ELSE CASE (assert_state) IS WHEN INIT_STATE => IF (test_expr = start_state) THEN assert_state := CHECK_STATE; r_next_state := next_state; END IF; WHEN CHECK_STATE => -- Count clock ticks IF (test_expr /= start_state) THEN assert_state := INIT_STATE; -- Check that the property is true IF (test_expr /= r_next_state) THEN valid <= '0'; END IF; END IF; END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_UNCHANGE -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_UNCHANGE - Clock bounded window expecting a change -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; use std.textio.all; use ieee.std_logic_textio.all; ENTITY assert_unchange IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; num_cks: INTEGER := 1; flag: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT UNCHANGE VIOLATION"); PORT (clk, reset_n: IN std_ulogic; start_event: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_unchange; ARCHITECTURE ovl OF assert_unchange IS TYPE stateT IS (UNCHANGE_START, UNCHANGE_CHECK); CONSTANT FLAG_IGNORE_NEW_START: INTEGER := 0; CONSTANT FLAG_RESET_ON_START : INTEGER := 1; CONSTANT FLAG_ERR_ON_START : INTEGER := 2; -- SIGNAL valid: std_ulogic := '1'; SIGNAL flag_error: std_ulogic := '0'; SIGNAL flag_para_error: std_ulogic := '0'; SIGNAL rst_n: std_ulogic; SIGNAL ii: INTEGER; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); ASSERT flag_error = '0' REPORT msg & " : illegal start event" SEVERITY ovlSevTab(severity_level); ASSERT flag_para_error = '0' REPORT msg & " : illegal flag parameter" SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := UNCHANGE_START; VARIABLE r_change: std_ulogic := '0'; VARIABLE r_test_expr : UNSIGNED((width-1) DOWNTO 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; -- IF (rst_n = '0') THEN r_state := UNCHANGE_START; r_change := '0'; valid <= '1'; flag_error <= '0'; flag_para_error <= '0'; r_test_expr := test_expr; ELSE CASE (r_state) IS WHEN UNCHANGE_START => IF (start_event = '1') THEN r_change := '0'; r_state := UNCHANGE_CHECK; r_test_expr := test_expr; ii <= num_cks; END IF; WHEN UNCHANGE_CHECK => -- Count clock ticks IF (start_event = '1') THEN CASE (flag) IS WHEN FLAG_IGNORE_NEW_START => IF (ii > 0) THEN ii <= ii-1; END IF ; WHEN FLAG_RESET_ON_START => ii <= num_cks; WHEN FLAG_ERR_ON_START => flag_error <= '1'; WHEN OTHERS => flag_para_error <= '1'; END CASE; ELSIF (ii > 0) THEN ii <= ii-1; END IF; -- // Check that the property is true IF (r_test_expr /= test_expr) THEN r_change := '1'; END IF; -- -- go to start state on last check IF ((ii = 1) AND NOT((start_event = '1') AND (flag = FLAG_RESET_ON_START))) THEN r_state := UNCHANGE_START; END IF; -- Check that the property is true IF ((r_change = '1') OR (r_test_expr /= test_expr)) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; -- r_test_expr := test_expr; END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_WIN_CHANGE -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_WIN_CHANGE - Event bounded window expecting a change -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_win_change IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT WIN CHANGE VIOLATION"); PORT (clk, reset_n: IN std_ulogic; start_event: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0); end_event: IN std_ulogic); END assert_win_change; ARCHITECTURE ovl OF assert_win_change IS TYPE stateT IS (WIN_CHANGE_START, WIN_CHANGE_CHECK); -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := WIN_CHANGE_START; VARIABLE r_change: std_ulogic := '0'; VARIABLE r_test_expr : UNSIGNED((width-1) DOWNTO 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN r_state := WIN_CHANGE_START; r_change := '0'; ELSE CASE (r_state) IS WHEN WIN_CHANGE_START => IF (start_event = '1') THEN r_change := '0'; r_state := WIN_CHANGE_CHECK; r_test_expr := test_expr; END IF; WHEN WIN_CHANGE_CHECK => -- Count clock ticks IF (r_test_expr /= test_expr) THEN r_change := '1'; END IF; IF (end_event = '1') THEN r_state := WIN_CHANGE_START; -- Check that the property is true IF ((r_change = '0') AND (r_test_expr = test_expr)) THEN valid <= '0'; END IF; END IF; r_test_expr := test_expr; END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_WIN_UNCHANGE -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_WIN_UNCHANGE - Event bounded window expecting a change -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_win_unchange IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT WIN UNCHANGE VIOLATION"); PORT (clk, reset_n: IN std_ulogic; start_event: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0); end_event: IN std_ulogic); END assert_win_unchange; ARCHITECTURE ovl OF assert_win_unchange IS TYPE stateT IS (WIN_UNCHANGE_START, WIN_UNCHANGE_CHECK); -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := WIN_UNCHANGE_START; VARIABLE r_unchange: std_ulogic := '1'; VARIABLE r_test_expr : UNSIGNED((width-1) DOWNTO 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN r_state := WIN_UNCHANGE_START; r_unchange := '1'; r_test_expr := test_expr; ELSE CASE (r_state) IS WHEN WIN_UNCHANGE_START => IF (start_event = '1') THEN r_unchange := '1'; r_state := WIN_UNCHANGE_CHECK; r_test_expr := test_expr; END IF; WHEN WIN_UNCHANGE_CHECK => -- Count clock ticks IF (r_test_expr /= test_expr) THEN r_unchange := '0'; END IF; IF (end_event = '1') THEN r_state := WIN_UNCHANGE_START; END IF; -- Check that the property is true IF ((r_unchange = '0') OR (r_test_expr /= test_expr)) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; r_test_expr := test_expr; END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_WINDOW -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_WINDOW - An event bounded (window) invariant concurrent -- assertion to ensure that a variable (or expression) -- remains TRUE. -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_window IS GENERIC (severity_level: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT WINDOW VIOLATION"); PORT (clk, reset_n: IN std_ulogic; start_event: IN std_ulogic; test_expr: IN std_ulogic; end_event: IN std_ulogic); END assert_window; ARCHITECTURE ovl OF assert_window IS TYPE stateT IS (WINDOW_START, WINDOW_CHECK); -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE r_state : stateT := WINDOW_START; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN r_state := WINDOW_START; valid <= '1'; ELSE CASE (r_state) IS WHEN WINDOW_START => IF (start_event = '1') THEN r_state := WINDOW_CHECK; END IF; WHEN WINDOW_CHECK => IF (end_event = '1') THEN r_state := WINDOW_START; else IF (test_expr /= '1') THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; END IF; END CASE; END IF; END PROCESS; -- synopsys translate_on END ovl; -- -- /* { -- --------------------------------------------------------------------------- -- -- ASSERT_ZERO_ONE_HOT -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_ZERO_ONE_HOT - An invariant concurrent assertion to ensure -- that only one std_ulogic of a variable is active -- high or the variable is zero. -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_zero_one_hot IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 32; options: INTEGER := 0; msg: STRING := "ASSERT ZERO ONE HOT VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_zero_one_hot; ARCHITECTURE ovl OF assert_zero_one_hot IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN valid <= '1'; ELSE IF (((+test_expr) = CONV_STD_LOGIC_VECTOR(0,width)) OR (((+test_expr) AND (test_expr - 1)) = CONV_STD_LOGIC_VECTOR(0,width))) THEN valid <= '1'; ELSE valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; ----------------------------------------------------------------------------- -- -- ASSERT_NEXT -- ----------------------------------------------------------------------------- -- NAME -- ASSERT_NEXT - Checks that "start_event" is asserted, after "num_cks" -- cycles "test_expr" will be asserted, or in logical -- terms, where X denotes the next cycle operator, -- "start_event => X^num_cks (test_expr)" -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_next IS GENERIC (severity_level: INTEGER := 0; num_cks: INTEGER := 1; check_overlapping: std_ulogic := '1'; only_if: std_ulogic := '0'; options: INTEGER := 0; msg: STRING := "ASSERT NEXT VIOLATION"); PORT (clk, reset_n: IN std_ulogic; start_event: IN std_ulogic; test_expr: IN std_ulogic); END assert_next; ARCHITECTURE ovl OF assert_next IS CONSTANT msg_ov: STRING := msg & " : illegal overlapping condition detected"; CONSTANT msg_st: STRING := msg & " : test_expr without start_event"; CONSTANT msg_te: STRING := msg & " : start_event without test_expr"; -- CONSTANT ZERO : UNSIGNED((num_cks-1) DOWNTO 0) := (OTHERS => '0'); CONSTANT ONE : UNSIGNED((num_cks-1) DOWNTO 0) := ZERO + 1; -- SIGNAL monitor : UNSIGNED((num_cks-1) DOWNTO 0) := (OTHERS => '0'); SIGNAL monitor_1 : UNSIGNED((num_cks-1) DOWNTO 0) := (OTHERS => '0'); SIGNAL overlap_err, start_error, test_error : std_ulogic := '0'; -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT overlap_err = '0' REPORT msg_ov SEVERITY ovlSevTab(severity_level); ASSERT start_error = '0' REPORT msg_st SEVERITY ovlSevTab(severity_level); ASSERT test_error = '0' REPORT msg_te SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- -- parameter only_if=0; -- if 1, test_expr can only appear if a corresponding -- -- start_event occurs -- monitor_1 <= SHL(monitor, ONE); -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; overlap_err <= '0'; start_error <= '0'; test_error <= '0'; IF (rst_n = '0') THEN monitor <= ZERO; ELSE if (start_event = '1') THEN monitor <= UNSIGNED(std_logic_vector(monitor_1) OR std_logic_vector(ONE)); ELSE monitor <= monitor_1; END IF; IF ((check_overlapping = '0') AND (monitor_1 /= ZERO) AND (start_event = '1')) THEN overlap_err <= '1'; END IF; IF ((only_if = '1') AND (monitor(num_cks-1) = '0') AND (test_expr = '1')) THEN start_error <= '1'; END IF; IF ((monitor(num_cks-1) = '1') AND (test_expr = '0')) THEN test_error <= '1'; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; ----------------------------------------------------------------------------- -- -- ASSERT_FRAME -- ----------------------------------------------------------------------------- -- NAME -- ASSERT_FRAME - Ensure cycle time relationship between start_event -- and test_expr evaluating true. -- ASSERT_FRAME checks test_expr has 0->1 change within -- [min_cks, max_cks] frame after start_event has 0->1 change. -- -- USAGE -- assert_frame -- #(severity_level, min_cks, max_cks, flag, options, msg) -- inst_name (clk, reset_n, start_event, test_expr); -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_frame IS GENERIC (severity_level: INTEGER := 0; min_cks: INTEGER := 0; max_cks: INTEGER := 0; flag: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT FRAME VIOLATION"); PORT (clk, reset_n, start_event: IN std_ulogic; test_expr: IN std_ulogic); END assert_frame; -- ARCHITECTURE ovl OF assert_frame IS TYPE stateT IS (FRAME_START, FRAME_CHECK); -- CONSTANT FLAG_IGNORE_NEW_START: INTEGER := 0; CONSTANT FLAG_RESET_ON_START: INTEGER := 1; CONSTANT FLAG_ERR_ON_START: INTEGER := 2; CONSTANT msg_st: STRING := msg & " : illegal start event"; -- SIGNAL r_test_expr: std_ulogic := '0'; SIGNAL r_state: stateT := FRAME_START; SIGNAL r_start_event: std_ulogic := '1'; SIGNAL valid: std_ulogic := '1'; SIGNAL start_ok : std_ulogic := '1'; -- SIGNAL ii: INTEGER := 0; SIGNAL rst_n: std_ulogic; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); ASSERT start_ok = '1' REPORT msg_st SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE numClks: INTEGER := 0; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; r_start_event <= start_event; r_test_expr <= test_expr; -- valid <= '1'; start_ok <= '1'; -- IF (rst_n = '0') THEN r_state <= FRAME_START; ELSE IF (r_state = FRAME_START) THEN IF ((max_cks = 0) AND (test_expr = '0')) THEN valid <= '0'; ELSIF (NOT((min_cks = 0) AND (r_test_expr = '0') AND (test_expr = '1')) AND ((r_start_event = '0') AND (start_event = '1'))) THEN r_state <= FRAME_CHECK; ii <= max_cks; END IF; ELSIF (r_state = FRAME_CHECK) THEN -- Count clock ticks IF ((r_start_event = '0') AND (start_event = '1')) THEN IF ((flag = FLAG_IGNORE_NEW_START) AND (ii > 0)) THEN ii <= ii-1; ELSIF (flag = FLAG_RESET_ON_START) THEN ii <= max_cks; ELSIF (flag = FLAG_ERR_ON_START) THEN r_state <= FRAME_START; start_ok <= '0'; END IF; ELSIF (ii > 0) THEN ii <= ii-1; END IF; -- go to start state on last check IF ((ii = 1) OR ((r_test_expr = '0') AND (test_expr = '1'))) THEN r_state <= FRAME_START; -- Check that the property is false numClks := max_cks - ii + 1; IF (NOT((numClks >= min_cks) AND (numClks <= max_cks) AND ((r_test_expr = '0') AND (test_expr = '1')))) THEN valid <= '0'; END IF; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; ----------------------------------------------------------------------------- -- -- ASSERT_IMPLICATION -- ----------------------------------------------------------------------------- -- NAME -- ASSERT_IMPLICATION - An invariant concurrent assertion to ensure -- that a logical implication always evaluates TRUE. -- -- USAGE -- assert_implication [#(severity_level, options, msg)] -- inst_name (clk, reset_n, antecendent_expr, consequent_expr); -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_implication IS GENERIC (severity_level: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT IMPLICATION VIOLATION"); PORT (clk, reset_n: IN std_ulogic; antecendent_expr, consequent_expr: IN std_ulogic); END assert_implication; -- ARCHITECTURE ovl OF assert_implication IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '1') THEN IF NOT ((antecendent_expr = '0') OR (consequent_expr = '1')) THEN valid <= '0'; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; ----------------------------------------------------------------------------- -- -- ASSERT_QUIESCENT_STATE -- ----------------------------------------------------------------------------- -- NAME -- ASSERT_QUIESCENT_STATE - A concurrent assertion that will -- verify a state machine (variable or expression) is in a -- known specified state when queried via activating a -- 'sample_event' expression or global -- ASSERT_END_OF_SIMULATION macro reference signal. -- -- USAGE -- assert_quiescent_state #(severity_level, width, options, msg) -- inst_name (clk, reset_n, state_expr, check_value, -- sample_event); -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_quiescent_state IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT QUIESCENT_STATE VIOLATION"; ASSERT_END_OF_SIMULATION: std_ulogic := '0'); PORT (clk, reset_n: IN std_ulogic; state_expr, check_value: IN UNSIGNED((width-1) DOWNTO 0); sample_event: IN std_ulogic); END assert_quiescent_state; ARCHITECTURE ovl OF assert_quiescent_state IS -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; -- SIGNAL r_sample_event: std_ulogic := '0'; SIGNAL r_EOS : std_ulogic := '0'; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; r_sample_event <= sample_event; IF (ASSERT_END_OF_SIMULATION = '1') THEN r_EOS <= ovl_END_OF_SIMULATION_SIGNAL; END IF; IF (rst_n = '1') THEN IF ((r_sample_event = '0') AND (sample_event = '1') AND (state_expr /= check_value)) THEN valid <= '0'; ELSIF ((ASSERT_END_OF_SIMULATION = '1') AND (r_EOS = '0') AND (ovl_END_OF_SIMULATION_SIGNAL = '1')) THEN valid <= '0'; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; ----------------------------------------------------------------------------- -- -- ASSERT_ONE_COLD -- ----------------------------------------------------------------------------- -- NAME -- ASSERT_ONE_COLD - An invariant concurrent assertion to ensure -- only one bit of the 'test_expr' variable is -- active low. -- -- USAGE -- assert_one_cold #(severity_level, width, inactive [, options, msg]) -- inst_name ( clk, reset_n, test_expr ); -- -- inactive = 0 allows inactive state of test_expr to be all zeros -- inactive = 1 allows inactive state of test_expr to be all ones -- inactive = 2 (default) specifies no inactive state is allowed -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_one_cold IS GENERIC (severity_level: INTEGER := 0; width: INTEGER := 32; inactive: INTEGER := 2; options: INTEGER := 0; msg: STRING := "ASSERT ONE COLD VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN UNSIGNED((width-1) DOWNTO 0)); END assert_one_cold; -- ARCHITECTURE ovl OF assert_one_cold IS CONSTANT ZERO : UNSIGNED((width-1) DOWNTO 0) := (OTHERS => '0'); CONSTANT ONES : UNSIGNED((width-1) DOWNTO 0) := (OTHERS => '1'); CONSTANT ONE : UNSIGNED((width-1) DOWNTO 0) := ZERO + 1; -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; -- BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE test_expr_i: UNSIGNED((width-1) DOWNTO 0); VARIABLE test_expr_i_1: UNSIGNED((width-1) DOWNTO 0); BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '1') THEN -- test_expr_i := UNSIGNED(NOT std_logic_vector(test_expr)); test_expr_i_1 := test_expr_i - ONE; -- IF (test_expr = ZERO) THEN IF (inactive /= 0) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; ELSIF (test_expr = ONES) THEN IF (inactive /= 1) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; ELSIF (UNSIGNED(std_logic_vector(test_expr_i) AND std_logic_vector(test_expr_i_1)) /= ZERO) THEN valid <= '0'; ASSERT false REPORT msg SEVERITY ovlSevTab(severity_level); END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; ----------------------------------------------------------------------------- -- -- ASSERT_CYCLE_SEQUENCE -- ----------------------------------------------------------------------------- -- NAME -- ASSERT_CYCLE_SEQUENCE - if "necessary_condition" is 0, this -- assertion checks that if all num_cks-1 first events of -- "event_sequence" are true, then the last one -- ("event_sequence[0]") must occur. -- -- If "necessary_condition" is 1, this assertion checks that -- once the first event ("event_sequence[num_cks-1]") occurs, -- all the remaining ones must occur. -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_cycle_sequence IS GENERIC (severity_level: INTEGER := 0; num_cks: INTEGER := 1; necessary_condition: std_ulogic := '0'; options: INTEGER := 0; msg: STRING := "ASSERT CYCLE SEQUENCE VIOLATION"); PORT (clk, reset_n: IN std_ulogic; event_sequence: IN UNSIGNED((num_cks-1) DOWNTO 0)); END assert_cycle_sequence; -- ARCHITECTURE ovl OF assert_cycle_sequence IS CONSTANT num_cks_1: INTEGER := num_cks - 1; CONSTANT num_buf_1: INTEGER := (num_cks_1+1)*num_cks_1/2; SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS CONSTANT ZERO: UNSIGNED(num_buf_1 DOWNTO 0) := (OTHERS => '0'); VARIABLE pipe_regs: UNSIGNED(num_buf_1 DOWNTO 0) := (OTHERS => '0'); VARIABLE jj, nn, lim, start: INTEGER; VARIABLE and_res: std_ulogic; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n = '0') THEN pipe_regs := ZERO; ELSE IF (num_cks = 1) THEN -- same as assert_always() IF (event_sequence(0) = '0') THEN -- check error valid <= '0'; END IF; ELSE IF (necessary_condition = '1') THEN lim := 1; ELSE lim := num_cks_1; END IF; nn := 0; jj := 0; start := 0; FOR pp IN num_cks_1 DOWNTO lim LOOP nn := nn + 1; start := start + nn; jj := start; and_res := '1'; -- get preconditon with and_res FOR ii IN nn TO (pp+nn-1) LOOP and_res := and_res AND pipe_regs(jj); jj := jj + ii; END LOOP; IF ((and_res = '1') AND (event_sequence(num_cks_1 - pp) = '0')) THEN -- check error valid <= '0'; END IF; END LOOP; FOR ii IN 0 TO (num_buf_1 - 1) LOOP -- update pipes pipe_regs(ii) := pipe_regs(ii+1); END LOOP; jj := 1; FOR ii IN 1 TO num_cks_1 LOOP pipe_regs(jj) := event_sequence(ii); jj := jj + ii + 1; END LOOP; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; ----------------------------------------------------------------------------- -- -- ASSERT_WIDTH -- ----------------------------------------------------------------------------- -- NAME -- ASSERT_WIDTH - An invariant concurrent assertion to ensure -- ----------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_width IS GENERIC (severity_level: INTEGER := 0; min_cks, max_cks: INTEGER := 1; options: INTEGER := 0; msg: STRING := "ASSERT WIDTH VIOLATION"); PORT (clk, reset_n: IN std_ulogic; test_expr: IN std_ulogic); END assert_width; -- ARCHITECTURE ovl OF assert_width IS TYPE stateT IS (WIDTH_START, WIDTH_CKMIN, WIDTH_CKMAX, WIDTH_IDLE); -- SIGNAL r_test_expr: std_ulogic := '0'; SIGNAL r_state: stateT := WIDTH_START; -- SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; SIGNAL num_cks : INTEGER := 0; SIGNAL ii: INTEGER; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS VARIABLE min: INTEGER := min_cks; VARIABLE max: INTEGER := max_cks; BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; r_test_expr <= test_expr; IF (rst_n = '0') THEN r_state <= WIDTH_START; r_test_expr <= '0'; num_cks <= 0; ELSE IF (r_state = WIDTH_START) THEN IF ((r_test_expr = '0') AND (test_expr = '1')) THEN num_cks <= 1; IF (min_cks > 0) THEN -- any max range legal r_state <= WIDTH_CKMIN; ELSIF (max_cks >0) THEN r_state <= WIDTH_CKMAX; END IF; END IF; ELSIF (r_state = WIDTH_CKMIN) THEN IF (test_expr = '1') THEN num_cks <= num_cks + 1; IF (num_cks >= min_cks) THEN IF (max_cks > 0) THEN r_state <= WIDTH_CKMAX; ELSE r_state <= WIDTH_IDLE; END IF; END IF; ELSIF (num_cks < min_cks) THEN valid <= '0'; --error ELSE r_state <= WIDTH_START; END IF; ELSIF (r_state = WIDTH_CKMAX) THEN IF (test_expr = '1') THEN num_cks <= num_cks + 1; IF (num_cks >= max_cks) THEN valid <= '0'; ELSE r_state <= WIDTH_IDLE; END IF; ELSIF (num_cks > max_cks) THEN valid <= '0'; ELSE r_state <= WIDTH_START; END IF; ELSIF (r_state = WIDTH_IDLE) THEN IF (test_expr = '0') THEN r_state <= WIDTH_START; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl; -- --------------------------------------------------------------------------- -- -- ASSERT_ALWAYS_ON_EDGE -- -- --------------------------------------------------------------------------- -- NAME -- ASSERT_ALWAYS_ON_EDGE - An invariant concurrent assertion to ensure -- that its argument always evaluates TRUE -- -- --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE work.ovl_assertlib.ALL; ENTITY assert_always_on_edge IS GENERIC (severity_level: INTEGER := 0; edge_type: INTEGER := 0; options: INTEGER := 0; msg: STRING := "ASSERT ALWAYS ON EDGE VIOLATION"); PORT (clk, reset_n, sampling_event, test_expr: IN std_ulogic); END assert_always_on_edge; ARCHITECTURE ovl OF assert_always_on_edge IS SIGNAL valid: std_ulogic := '1'; SIGNAL rst_n: std_ulogic; SIGNAL sampling_event_fired : std_ulogic; SIGNAL sampling_event_prev : std_ulogic := '0'; CONSTANT OVL_NOEDGE : INTEGER := 0; CONSTANT OVL_POSEDGE : INTEGER := 1; CONSTANT OVL_NEGEDGE : INTEGER := 2; CONSTANT OVL_ANYEDGE : INTEGER := 3; BEGIN -- synopsys translate_off -- // synopsys template -- // ovl assertion_library -- ASSERT valid = '1' REPORT msg SEVERITY ovlSevTab(severity_level); -- rst_n <= ovl_reset_n when (ovl_reset_n_enable = '1') else reset_n; -- PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk = '1'; valid <= '1'; IF (rst_n /= '0') THEN -- Capture Sampling Event @Clock for rising edge detections sampling_event_prev <= sampling_event; IF (test_expr /= '1') THEN IF (edge_type = OVL_NOEDGE) THEN valid <= '0'; ELSIF ((edge_type = OVL_POSEDGE) AND (sampling_event_prev = '0') AND (sampling_event = '1')) THEN valid <= '0'; ELSIF ((edge_type = OVL_NEGEDGE) AND (sampling_event_prev = '1') AND (sampling_event = '0')) THEN valid <= '0'; ELSIF ((edge_type = OVL_ANYEDGE) AND (sampling_event_prev /= sampling_event)) THEN valid <= '0'; END IF; END IF; END IF; END PROCESS; -- synopsys translate_on END ovl;