LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

--
-- Make a OVL package for global reset signal
--
PACKAGE ovl_assertlib IS
--
  FUNCTION ovlSevTab ( idx: INTEGER) return severity_level;
--
  SIGNAL ovl_reset_n: std_ulogic := '1';
  SIGNAL ovl_reset_n_enable: std_ulogic := '0';
  SIGNAL ovl_end_of_simulation_signal: std_ulogic := '0';
--
  FUNCTION xorr ( V: unsigned) return std_ulogic;
  FUNCTION to_std ( V: boolean) return std_ulogic;
  FUNCTION stdv_to_unsigned ( V: std_logic_vector) return unsigned;
  FUNCTION unsigned_to_stdv ( V: unsigned) return std_logic_vector;
--
COMPONENT assert_always
  GENERIC (severity_level: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT ALWAYS VIOLATION");
  PORT (clk, reset_n, test_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_change
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           num_cks: INTEGER := 1;
           flag: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT CHANGE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        start_event: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_next
  GENERIC (severity_level: INTEGER := 0;
           num_cks: INTEGER := 1;
           check_overlapping: INTEGER := 1;
           only_if: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT NEXT VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        start_event: IN std_ulogic;
        test_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_decrement
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           value: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT DECREMENT VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_delta
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           min: INTEGER := 1;
           max: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT DELTA VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_even_parity
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT EVEN PARITY VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_frame
  GENERIC (severity_level: INTEGER := 0;
           min_cks: INTEGER := 1;
           max_cks: INTEGER := 1;
           flag: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT FRAME VIOLATION");
  PORT (clk, reset_n, start_event: IN std_ulogic;
        test_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_handshake
  GENERIC (severity_level: INTEGER := 0;
           min_ack_cycle: INTEGER := 0;
           max_ack_cycle: INTEGER := 0;
           req_drop: INTEGER := 0;
           deassert_count: INTEGER := 0;
           max_ack_length: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT HANDSHAKE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        req, ack: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_implication
  GENERIC (severity_level: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT HANDSHAKE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        antecendent_expr, consequent_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_increment
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           value: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT INCREMENT VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_never
  GENERIC (severity_level: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT NEVER VIOLATION");
  PORT (clk, reset_n, test_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_no_overflow
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           min: INTEGER := 0;
           max: INTEGER := INTEGER'high;
           options: INTEGER := 0;
           msg: STRING := "ASSERT NO OVERFLOW VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_no_transition
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT NO TRANSITION VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0);
        start_state: IN UNSIGNED((width-1) DOWNTO 0);
        end_state: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_no_underflow
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           min: INTEGER := 0;
           max: INTEGER := INTEGER'high;
           options: INTEGER := 0;
           msg: STRING := "ASSERT NO UNDERFLOW VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_odd_parity
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT ODD PARITY VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_proposition
  GENERIC (severity_level: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT PROPOSITION VIOLATION");
  PORT (reset_n, test_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_quiescent_state
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT QUIESCENT_STATE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        state_expr, check_value: IN UNSIGNED((width-1) DOWNTO 0);
        sample_event: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_prop_one_hot
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 32;
           inactive: INTEGER := 2;
           options: INTEGER := 0;
           msg: STRING := "ASSERT PROPOSITIONAL ONE HOT VIOLATION");
  PORT (reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_prop_one_cold
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 32;
           inactive: INTEGER := 2;
           options: INTEGER := 0;
           msg: STRING := "ASSERT PROP ONE COLD VIOLATION");
  PORT (reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_prop_one_one_cold
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 32;
           inactive: INTEGER := 2;
           options: INTEGER := 0;
           msg: STRING := "ASSERT PROPOSITIONAL ONE ONE COLD VIOLATION");
  PORT (reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_prop_zero_one_hot
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 32;
           options: INTEGER := 0;
           msg: STRING := "ASSERT PROPOSITIONAL ZERO ONE HOT VIOLATION");
  PORT (reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_range
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           min: INTEGER := 1;
           max: INTEGER := INTEGER'high;
           options: INTEGER := 0;
           msg: STRING := "ASSERT ON");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_time
  GENERIC (severity_level: INTEGER := 0;
           num_cks: INTEGER := 1;
           flag: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT TIME VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        start_event: IN std_ulogic;
        test_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_transition
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT TRANSITION VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0);
        start_state: IN UNSIGNED((width-1) DOWNTO 0);
        end_state: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_unchange
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           num_cks: INTEGER := 1;
           flag: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT UNCHANGE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        start_event: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_win_change
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT WIN CHANGE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        start_event: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0);
        end_event: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_win_unchange
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT WIN UNCHANGE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        start_event: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0);
        end_event: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_window
  GENERIC (severity_level: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT WINDOW VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        start_event: IN std_ulogic;
        test_expr: IN std_ulogic;
        end_event: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_one_cold
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 32;
           inactive: INTEGER := 2;
           options: INTEGER := 0;
           msg: STRING := "ASSERT ONE COLD VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_one_hot
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 32;
           options: INTEGER := 0;
           msg: STRING := "ASSERT ONE HOT VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_zero_one_hot
  GENERIC (severity_level: INTEGER := 0;
           width: INTEGER := 32;
           options: INTEGER := 0;
           msg: STRING := "ASSERT ZERO ONE HOT VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN UNSIGNED((width-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_cycle_sequence
  GENERIC (severity_level: INTEGER := 0;
           num_cks: INTEGER := 1;
           necessary_condition: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT CYCLE SEQUENCE VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        event_sequence: IN UNSIGNED((num_cks-1) DOWNTO 0));
END COMPONENT;
--
COMPONENT assert_width
  GENERIC (severity_level: INTEGER := 0;
           min_cks, max_cks: INTEGER := 1;
           options: INTEGER := 0;
           msg: STRING := "ASSERT WIDTH VIOLATION");
  PORT (clk, reset_n: IN std_ulogic;
        test_expr: IN std_ulogic);
END COMPONENT;
--
COMPONENT assert_always_on_edge
  GENERIC (severity_level: INTEGER := 0;
           edge_type: INTEGER := 0;
           options: INTEGER := 0;
           msg: STRING := "ASSERT ASSERT_ALWAYS_ON_EDGE VIOLATION");
  PORT (clk, reset_n, sampling_event, test_expr: IN std_ulogic);
END COMPONENT;
--

END ovl_assertlib ;


PACKAGE body ovl_assertlib IS

  FUNCTION ovlSevTab ( idx: INTEGER) return severity_level IS
  BEGIN
    CASE (idx) IS
      WHEN 0 => RETURN failure;
      WHEN 1 => RETURN error;
      WHEN 2 => RETURN warning;
      WHEN 3 => RETURN note;
      WHEN OTHERS =>
                ASSERT false REPORT "In ovlSevTab(idx): idx not in 0..3" SEVERITY error;
                RETURN failure;
    END CASE;
  END ovlSevTab;

  FUNCTION to_std ( V: boolean) return std_ulogic IS
  BEGIN
    IF (V) THEN  
      RETURN '1';
    ELSE
      RETURN '0';
    END IF;
  END to_std;

  FUNCTION xorr ( V: unsigned) return std_ulogic IS
    variable reduce: std_ulogic;
  BEGIN
    FOR i in V'range LOOP
      IF i = V'left THEN
        reduce := V(i);
      ELSE
        reduce := reduce XOR V(i);
      END IF;
    END LOOP;
    RETURN reduce;
  END xorr;

  FUNCTION stdv_to_unsigned ( V: std_logic_vector) return unsigned IS
    variable result: unsigned(V'range);
  BEGIN
    FOR i in V'range LOOP
      result(i) := V(i);
    END LOOP;
    RETURN result;
  END stdv_to_unsigned;

  FUNCTION unsigned_to_stdv ( V: unsigned) return std_logic_vector IS
    variable result: std_logic_vector(V'range);
  BEGIN
    FOR i in V'range LOOP
      result(i) := V(i);
    END LOOP;
    RETURN result;
  END unsigned_to_stdv;

END ovl_assertlib ;