Re: Fw: Next meeting of the System Verilog Assertion Sub-committee

Subject: Re: Fw: Next meeting of the System Verilog Assertion Sub-committee
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Mon Jul 22 2002 - 23:29:43 PDT

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faisal,

i thought that at the last meeting we had agreed on the week after (august
1). is this a mistake, or was there a change? i will be on vacation this
thursday, july 25.

cindy.

Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com

"Faisal Haqaue" <fhaque@cisco.com>@eda.org on 22/07/2002 18:45:00

Please respond to "Faisal Haqaue" <fhaque@cisco.com>

Sent by: owner-assertion@eda.org

To: <assertion@eda.org>
cc:
Subject: Fw: Next meeting of the System Verilog Assertion Sub-committee

We will have the next meeting of the SV-AC sub-committee on Thursday July
25th at 10:00 am PDT
Agenda:
    DWG
    Identify owner of requirements document
    Requirements review dates
    Coordination
    Next Meeting Date

Thanks.
-Faisal

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