Subject: RE: Fitz's Action Items for 7/22 Meeting
From: Cindy Eisner (EISNER@il.ibm.com)
Date: Mon Jul 22 2002 - 05:55:33 PDT
tom,
thanks. one question:
how is the direction of the interface signals determined from the verilog
source? for instance, in the example without interfaces on page 66, output
signals of cpuMod are input signals to memMod, and vice versa. but in the
example with interfaces on page 67, neither the interface itself nor either
of the modules indicates whether the signals are inputs, outputs, or
inouts. it seems that the answer is to use modport, but i don't see
anywhere that this is required. for instance, the example on page 67 does
not use it.
regards,
cindy.
Cindy Eisner
Formal Methods Group Tel: +972-4-8296-266
IBM Haifa Research Laboratory Fax: +972-4-8296-114
Haifa 31905, Israel e-mail:
eisner@il.ibm.com
"Tom Fitzpatrick" <fitz@co-design.com>@eda.org on 22/07/2002 15:27:16
Sent by: owner-assertion@eda.org
To: Cindy Eisner/Haifa/IBM@IBMIL
cc: <assertion@eda.org>
Subject: RE: Fitz's Action Items for 7/22 Meeting
Hi Cindy,
An Interface is one of the new modelling constructs added to SystemVerilog
from Superlog. It allows encapsulation of communication (signals/protocols)
similarly to how modules encapsulate functionality, and is explained in
detail in section 13 of the SystemVerilog LRM, which you can get at
http://www.accellera.org/3.0_LRM.pdf.
Please let me know if you have any questions about interfaces.
Thanks,
-Tom
> -----Original Message-----
> From: owner-assertion@server.eda.org
> [mailto:owner-assertion@server.eda.org]On Behalf Of Cindy Eisner
> Sent: Sunday, July 21, 2002 2:16 AM
> To: Tom Fitzpatrick
> Cc: Adam Krolnik; assertion@server.eda.org
> Subject: RE: Fitz's Action Items for 7/22 Meeting
>
>
>
> tom, adam,
>
> i can't follow this discussion. apparently, it is a thread that was
> started in one of the other mailing lists. can you please tell us what
an
> interface is (and why it is instantiated only once) or point us to the
> relevant material?
>
> thanks,
>
> cindy.
>
> Cindy Eisner
> Formal Methods Group Tel: +972-4-8296-266
> IBM Haifa Research Laboratory Fax: +972-4-8296-114
> Haifa 31905, Israel e-mail:
> eisner@il.ibm.com
>
>
> "Tom Fitzpatrick" <fitz@co-design.com>@eda.org on 20/07/2002 00:17:37
>
> Sent by: owner-assertion@eda.org
>
>
> To: "Adam Krolnik" <krolnik@lsil.com>
> cc: <sv-bc@eda.org>, <sv-ec@eda.org>, <assertion@eda.org>
> Subject: RE: Fitz's Action Items for 7/22 Meeting
>
>
>
> Hi Adam,
>
> Actually, you've hit on one way that an interface is different from a
> module
> in this respect. Since the interface is only instantiated once even
though
> it may connect to multiple modules, or through multiple levels of
> hierarchy,
> any logic in the interface is only executed once. Therefore, if we
allowed
> instantiations of OVL modules in an interface, the OVL module
> would execute
> only once for each module instance.
>
> -Tom
>
> > -----Original Message-----
> > From: owner-assertion@server.eda.org
> > [mailto:owner-assertion@server.eda.org]On Behalf Of Adam Krolnik
> > Sent: Friday, July 19, 2002 5:03 PM
> > To: Tom Fitzpatrick
> > Cc: sv-bc@server.eda.org; sv-ec@server.eda.org;
assertion@server.eda.org
> > Subject: Re: Fitz's Action Items for 7/22 Meeting
> >
> >
> >
> > Hi Tom;
> >
> > You wrote:
> >
> > >This is certainly an area that can be discussed more, since we
> > may want to
> > >allow OVL modules to be instantiated in interfaces, for example.
> > There may
> > >be a way to define what a "passive" module is in this case, and
> > only allow
> > >passive modules to be instantiated in interfaces. Let's discuss.
> >
> > Yes, we do want OVL assertion (modules) to be placed in an interface
> > (in addition to Sugar assertions/SystemVerilog assertions.)
> >
> > But you are correct, modules with outputs (or anything driving a signal
> > in
> > an interface) will not work. [A signal modport'd to an input will have
a
> > conflict.]
> >
> > Extra points: Placing an assertion/OVL module in an interface will
cause
> > it to be
> > evaluated in each place where the interface is used, correct?
> >
> > It would be better to only simulate an assertion/OVL module once,
rather
> > than
> > at each usage.
> >
> >
> > Adam Krolnik
> > Verification Mgr.
> > LSI Logic Corp.
> > Plano TX. 75074
> >
>
>
>
>
>
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