Assertion Requirements and Donation

Subject: Assertion Requirements and Donation
From: Stephen Meier (Stephen.Meier@synopsys.com)
Date: Tue Jul 09 2002 - 07:43:08 PDT

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David Lacey and assertion committee members:

Synopsys would like to formally donate to the assertions committee the OpenVera Assertions language technology (OVA v2.0). The donation has been sent via Accellera TCC (Vassilios)

In support of this donation, Synopsys moves to suggest following as technical requirements for enhancing SystemVerilog assertions:

R1: add declarative form of assertions with ability to define sequences, time windows, implication

        R2: support directives to guide tool interpretation of assertion ( in OVA = assert, forbid, assume)
        R3: support synchronous clocking for R1
        R4: support set/reset of assertions for R1
        R5: support template definition and instantiation feature for assertions
        R6: support features for matching (first_match), restricting length (length)
        R7: support R1 in-lined within SystemVerilog code

In addition Synopsys suggests that following guidelines be followed for addressing the assertion requirements:
        M1: use Verilog syntax
        M2: support SystemVerilog language features
        M3: intuitive and easy to use language

Thanks for considering the requirements and donations.

Regards,
Steve Meier

Steve Meier (stephen.meier@synopsys.com) W: 650-584-4476, Cell: 408-393-8246

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