Subject: SV-CC Commmittee Email Reflector
From: David Lacey (dlacey@rsn.hp.com)
Date: Sat Jul 06 2002 - 12:56:12 PDT
Hi,
an SV-CC email reflector has started. I have not added anyone yet. Below you will find a call for starting this committee by Ghassan Khoory. I have asked him to start the committee. I am talking to potential chairman for this committee.
By the end of this week the new committee email reflectors will be on line (SV-CC, SV-EC, SV-BC).
You can subscribe to any of these new lists by sending an email to
majordomo@eda.org with the subject of subscribe. In the body of the email you can add one or all of the following:
subscribe sv-cc
subscribe sv-ec
subscribe sv-bc
end
If your prefer, you send an email to the chairs or me.
Both Cliff and Dave have started their committees (planned for Friday).
Ghassan Ghoory will start the sv-cc committee soon (next week or the week after).
David Lacey have called for a meeting on assertion. He will be c
ollecting an official assertion issue list. Please send him what you
believe is an issue with the SV 3.0 assertions.
I encourage meeting participants to have a teamwork spirit. Thank you
for supporting the chairs.
Thanks again for your help
-----Original Message-----
From: Ghassan Khoory [mailto:Ghassan.Khoory@synopsys.com]
Sent: Wednesday, June 26, 2002 11:11 PM
To: vlog-pp@eda.org; assertion@eda.org; accellera_bod@accellera.org
Subject: SV-CC Committee
Hi:
The Accellera standards committee has formed a sub committee for deciding on the requirement for a C/C++ interface to system verilog and additional API for coverage data.
We are looking for users of such environ
ment where the tight integration of C/C++ and Verilog is an integral part of their verification environment and methodology. Those users experience and requirement can help in defining the requirement for those interfaces into System Verilog.
In addition:
o Extending System Verilog language has implications on simulator interface
o New Technologies like Coverage and Assertions are an integral part of the simulator
o Need API to access important information like Coverage, Assertions to interface other tools with System Verilog simulators
o Comprehensive API Allows new visualization, debug and analysis tools and flows to be created and easily interfaced with System Verilog simulators
o Non standard simulator interfaces can delay adoption of enabling technologies or introduce high overhead using them
Please, forward this email to anyone you might know that can help in this committee. If interested, just reply to this email.
Thanks,
/gjk
Ghassan Khoory
Verification Technolog
y Group
Synopsys, Inc.
508-263-8073
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