Subject: SV-CC Committee
From: David Lacey (dlacey@rsn.hp.com)
Date: Wed Jun 26 2002 - 14:23:28 PDT
Hi:
The Accellera standards committee has formed a sub committee for
deciding on
the requirement for a C/C++ interface to system verilog and additional
API
for coverage data.
We are looking for users of such environment where the tight integration
of
C/C++ and Verilog is an integral part of their verification environment
and
methodology. Those users experience and requirement can help in defining
the
requirement for those interfaces into System Verilog.
In addition:
o Extending System Verilog language has implications on simulator
interface
o New Technologies like Coverage and Assertions are an integral part of
the
simulator
o Need API to access important information like Coverage, Assertions to
interface other tools with System Verilog simulators
o Comprehensive API Allows new visualization, debug and analysis tools
and
flows to be created and easily interfaced with System Verilog simulators
o Non standard simulator interfaces can delay adoption of enabling
technologies or introduce high overhead using them
Please, forward this email to anyone you might know that can help in
this
committee. If interested, just reply to this email.
Thanks,
/gjk
Ghassan Khoory
Verification Technology Group
Synopsys, Inc.
508-263-8073
-- David J. Lacey Email: dlacey@rsn.hp.com Phone: 972-497-4114
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