Subject: RE: Next OVL Meeting - Thursday May 4
From: Dennis Brophy (dennisb@model.com)
Date: Thu May 02 2002 - 11:21:14 PDT
Eric,
I think the date was corrected to May 9th. That's what I put in my
calendar.
-Dennis
-----Original Message-----
From: Erich Marschner [mailto:erichm@cadence.com]
Sent: Thursday, May 02, 2002 9:19 AM
To: David Lacey; Accellera Assertion
Subject: RE: Next OVL Meeting - Thursday May 4
Is anyone having any luck getting into this meeting? Or am I the only one
who is stuck on indefinite hold listening to Muzak?
Regards,
Erich
-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net
| -----Original Message-----
| From: David Lacey [mailto:dlacey@rsn.hp.com]
| Sent: Monday, April 29, 2002 3:14 PM
| To: Accellera Assertion
| Subject: Next OVL Meeting - Thursday May 4
|
|
|
| Now that we have completed our first round of efforts on the
| SystemVerilog assertion, I would like to get going on the OVL efforts
| again. So I am calling a meeting on Thursday, May 4,
| starting at 9:00
| AM PST.
|
| At this meeting, we will create a road map for the OVL that can be
| presented at DAC this year. Main items include:
|
| (a) building a library of procedural assertions based on the new
| SystemVerilog assertion construct,
| (b) Examine existing concurrent library and formalize
| definition (or
| create a sub-committee to do this),
| (c) Discuss enhancements proposed by Joe Richards from SGI
| (d) Discuss VHDL OVL Sub-committee (we have a few
| volunteers willing
| to
| get invoved in this effort based on the verification guild
| posting)
|
| Date: Thursday, May 4
| Time: 9:00am PT.
| Domestic Dial-In #: 888-621-9228
| Intl Dial-In #: 212-485-8161
| Room #: *9724231659*
|
| Thanks!
|
| David
|
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