Subject: Assertions Goals Revisited
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Apr 08 2002 - 04:44:13 PDT
Dear Assertion Committee members,
I want to thank everyone who have sent me emails to re-visit the goals of this committee.
In the last few weeks, this committee have worked hard in establishing Verilog assertion language constructs. Both the chair and the co-chair have worked hard to lead this effort. I do want to thank all of you for doing the best to meet the deadline.
Many of you have responded the last week to provide individual as well as their companies support for further development of assertions. As stated before, Accellera is leading a spectrum of verification standard. This committee is developing two important segments. First the language constructs, which we have focused on Verilog. Then the second part of the spectrum is OVL. The majority of this committee membership have/will support the effort of continual OVL improvement as well as Verilog language improvements. I want to thank the following companies or individuals who confirmed their support for such standardization. This include
1- Infineon.
2- Motorola.
3- CISCO.
4- SGI.
5- HP.
6- Verplex.
7- Cadence.
8- Real Intent.
9- Forte Design Systems.
10- Co-Design.
Based on the feedback I have received, we no have goals for OVL that David Lacey and Tom Fitzpatrick to lead the standardization of OVL in the following areas:
1- Next OVL Release:
a- Clean Up in terms of consistency as voiced by few users.
b- Implement OVL with the new Verilog assertion constructs.
c- Additional models?
2- Release to be planned with SystemVerilog 3.1
a- Verilog enhancement to support macro-like capability.
b- Re-implement OVL to support this macro-type concept.
I leave this now in your hands to discuss and plan.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
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