Subject: Re: Call for Final Vote on Assertion Spec (version 1.8)
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Apr 05 2002 - 14:38:12 PST
Good afternoon David;
I would ask that the vote be postponed until next week. It does
not seem that enough of the committee members will vote
on the final version.
If no, I am going to vote against the final spec for the
reason of consumption I brought up.
Assertions would not work where a variable time window
is required. Typically when you have a variable time window
you have some amount of pipelining (usually limited to a
maximum amount) that assertions would appear to work in this
capacity but would then fail to detect a problem.
I seems that to then write the correct assertion an unreasonable
amount of code would be required from the designer. This kind
of code is unreasonable because of it's size.
I have been able to convince designers to use assertions mainly
on the points of:
A. They are very easy to write - one (or a few) line statements.
B. They cut your debug time by 50%.
The proposed model would define a capability that may not be easily
extendable should we find out that we should have another model
instead.
I do like the rest of the specification - the current methodology
that I run would fit nicely if Verilog had this assertion feature
or if I switched to SystemVerilog.
Thanks.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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