Subject: Re: Question
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Apr 04 2002 - 10:31:02 PST
Ignoring that inputs may have # delay times...
always @(a or b or c or d) begin
if (a)
assert (b; c; d) @@(posedge clk);
end
Is similar to
always @(posedge clock)
begin
assert_strobe (a triggers (b;c;d));
end
Correct?
A second question that leads to a potential false firing is:
What if A can be 2 cycles wide but B, C, D are not...
The assertion will run twice...
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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