Re: FW: Minutes of Assertion meeting 3/21/02


Subject: Re: FW: Minutes of Assertion meeting 3/21/02
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Mar 28 2002 - 08:06:19 PST


Hi Erich;

While you are on this subject comparing/contrasting the
two languages for temporal expressions.

How does each account for possible overlap of two expressions?
E.g. If A and B can occur at the same cycle or 1,2 cycles apart
how would each write this?

Also, what do each of these languages do to access past or
future values of signals/expressions?
E.g. No change on a clocked signal would involve comparing
the previous value with the current. I write this like

   delay(signal, 1) == signal

  THanks.

   Adam Krolnik
   Verification Mgr.
   LSI Logic Corp.
   Plano TX. 75074



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