Subject: end of simulation
From: Harry Foster (harry@verplex.com)
Date: Thu Mar 21 2002 - 15:03:40 PST
Did the SUPERLOG finish block (or what every it is
called) get donated as part of SystemVerilog? One of the
most valuable assertions we had in HP Richardson
was the assert_quiescent_state. Essentially, this
assertion had a PLI callback at the end of simulation
for consistency checking (ensure that state machines
were returned to proper states...ensure that there
weren't any outstanding transactions...ensure that
queues and FIFOs were empty, etc.). There were a
lot of problems we identified in simulation that would
not have been caught by any other means without
this assertions. Many problems were too complex for
formal or semi-formal analysis--this was an HP
verification secret weapon... ;-)
If the 'finish' block construct was not donated
to SystemVerilog, maybe we should add a system
task to perform this check at the end of simulation?
BTW--the PLI approach has really zero overhead in
simulation since we only use this as a callback at
the end of simulation (and don't visit it during
the course of simulation).
Best regards,
-Harry
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