Subject: Re: Assertions known from VHDL
From: Peter Flake (flake@co-design.com)
Date: Tue Mar 19 2002 - 05:02:40 PST
Hi Wolfgang,
In Verilog, the 'initial' block is used to execute statements once only,
after elaboration. So it could be used for assertions about parameter values.
The proposed assertions are called procedural, which is the Verilog term
for sequential code.
Peter.
At 11:09 AM 3/19/02 +0100, Wolfgang.Ecker@Infineon.Com wrote:
>Dear all,
>
>when reviewing the assertion proposal, two questions came up, when
>comparing assertins from Verilog/SystemVerilog with those of VHDL
>
>(1) Assertions in VHDL can be applied to generic values as well as
> to constants. Due to the semantic of VHDL, the assertions are
> executed once at begin of simulation only. The application is
> consistency checking of generic settings.
>
> In VERILOG, generics relate to defines or parameter. Can the
> proposed VERILOG assertions also applied to defines and/or parameter?
>
>(2) Assertions in VHDL can be included in sequential code and are then also
> executed in a sequential way. Applications are amongs others the check
> of parameters before an expression and the evaluation of the result of a
> parameter.
>
> Due to my knowledge, sequential assertions are not defined for VERILOG
> asserions but only object based asserstions. Is this true, and is there
> a reason for?
>
>regards,
>
>Wolfgang Ecker
This archive was generated by hypermail 2b28 : Tue Mar 19 2002 - 06:55:03 PST