Subject: Assertions known from VHDL
From: Wolfgang.Ecker@Infineon.Com
Date: Tue Mar 19 2002 - 02:09:57 PST
Dear all,
when reviewing the assertion proposal, two questions came up, when
comparing assertins from Verilog/SystemVerilog with those of VHDL
(1) Assertions in VHDL can be applied to generic values as well as
to constants. Due to the semantic of VHDL, the assertions are
executed once at begin of simulation only. The application is
consistency checking of generic settings.
In VERILOG, generics relate to defines or parameter. Can the
proposed VERILOG assertions also applied to defines and/or parameter?
(2) Assertions in VHDL can be included in sequential code and are then also
executed in a sequential way. Applications are amongs others the check
of parameters before an expression and the evaluation of the result of a
parameter.
Due to my knowledge, sequential assertions are not defined for VERILOG
asserions but only object based asserstions. Is this true, and is there
a reason for?
regards,
Wolfgang Ecker
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