Subject: Minutes of Wednesday, 3/13 meeting
From: Tom Fitzpatrick (fitz@co-design.com)
Date: Mon Mar 18 2002 - 14:02:39 PST
Hi All,
Here are the minutes of last Wednesday's meeting. On Thursday, some of us
met as part of the larger Verilog++ meeting, and we agreed to a schedule for
the overall SystemVerilog 3.0 standard. In order to meet this timeline and
get assertions included in SystemVerilog, we have until April 4th to get the
Assertions spec approved. Given the progress we made at the last meeting, I
think we may be able to do it before then, so I've scheduled the following
meetings:
Thursday, 3/21
Thursday, 3/28
Thursday, 4/4
all at 9am-11am PST on (405)244-5555 x3715
Attendees:
Tom Anderson (0-in)
Gail Dagan (Intel)
Simon Davidmann (Co-Design)
Tom Fitzpatrick (Co-Design)
Peter Flake (Co-Design)
Harry Foster (Verplex)
David Lacey (HP)
Prakash Narain (Real Intent)
Rajeev Ranjan (Real Intent)
Joe Richards (National?)
Richard Stolzman (Verplex)
Adam was not on the call live, but since he did such a good job in bringing
up questions/issues, we'll include him as having attended for the purposes
of keeping voting rights.
1. We voted on the priority of each section of the document and agreed to
work on the sections in the following order:
Immediate Assertions
Clocked Immediate Assertions
Strobed Assertions
Clocked Strobed Assertions
Expression Sequences
System Functions
Antecedent/Consequent
Resetting Assertions
Controlling Assertions
We then began going through the document. The significant change was that we
agreed to remove the "implicit clock" capability and require an explicit
"@@(posedge clk)" on sequential assertions to specify the step control. We
unanimously approved the Immediate and Strobed assertion sections with minor
modifications, which will be distributed shortly. We agreed on many of the
principles for Clocked and Clocked Strobed assertions, but we'll vote on
those sections on Thursday, after everyone has had a chance to review the
updated spec.
Other notes:
Immediate Assertions: cleaned up language to state that expressions are
evaluated like if conditions. True means known, non-zero value, so X,Z or 0
will fail.
We agreed that a default message shall always be printed in simulation when
an assertion fails. The $fatal,$error,$warning and $info system tasks allow
an additional message to be printed.
$error is now the default severity.
$fatal takes an argument that behaves like the arg to $finish.
I should have the updated document out tomorrow (Tuesday). Please take a
look at it before Thursday's meeting.
Thanks,
-Tom
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