Subject: Sequential Regular Expressions as Assertions
From: Harry Foster (harry@verplex.com)
Date: Mon Mar 18 2002 - 12:10:07 PST
As many of you know, the Accellera Formal Verification Committee is nearing
the end of its language selection process--scheduled for early April. The
two candidate languages (SUGAR and Extended CBV) both support a syntax for
expressing regular expressions. I would hate to see the SystemVerilog and
Formal Property Language syntax for the basic regular expression differ.
This would only introduce confusion in the industry and minimize
interoperability between the SystemVerilog assertions and the formal
property language.
I would like the assertion committee to serious consider delaying adding the
sequential regular expressions to the 3.0 SystemVerilog draft. We should be
able to add this construct to the 3.1 December draft and align regular
expression syntax between the two committees. The SystemVerilog regular
expressions would be a subset of the formal property language regular
expressions. However, I feel that the syntax should really be the same.
We can discuss this during our upcoming meeting.
-Harry
This archive was generated by hypermail 2b28 : Mon Mar 18 2002 - 12:13:27 PST