Subject: Assertion Committee Goals Revisited.
From: Vassilios.Gerousis@Infineon.Com
Date: Sun Mar 17 2002 - 14:21:33 PST
Dear Assertion Committee Members,
We have discussed the goals at 2:00 PM as was scheduled. Presents are Peter Flake, Harry Foster, David Lacey, Prakash, Rajive, Wolfgang, and Dennis. We discussed "last month" conduct by few members. We also revisited the Assertion Committee Goals. Here is a summary:
1- Conduct: It is important to emphasize that Accellera provide an open environment for members of different companies to come together and generate standards. It is important to work within these open meetings and not outside in terms of standard development. We understand the need to operate quickly, but any such activities must be reported and understood.
a- Everyone should understand that SystemVerilog, donated by Co-Design is now the property of Accellera. This means that it is available to anyone as an industry standard.
b- Work related to such a standard (extension or modification) within the committee belong to Accellera.
c- Any proprietary information or patented information cannot be disclosed unless, donation to Accellera id done first.
2- Goals Revisited:
a- Verilog Language Assertions: Verilog language extensions based on the donations from Co-design and Real Intent. Once the assertion committee (not the working group) vote on this donation, then it becomes the property of Accellera and it will be planned for inclusion in the SystemVerilog LRM. Please note that Verilog++ committee, will also discuss and approve the inclusion within SystemVerilog LRM.
b- OVL (High Level Assertion): These are library-based assertions built on Verilog Assertion Language constructs. From the user community points of view, these library are of high value and such it requires the cooperation of different vendors and users to develop and optimize
such a library. Please see action item below in regards to OVL.
c- Usage Model: Currently, OVL is a model-based library. A more powerful and flexible capability will be required to allow an improved way for building and using such high level constructs. The plan is for SystemVerilog 3.1 to provide such a mechanism (through a task or a function) that is non-blocking.
3- Action Item: It is important that every assertion member provide a position statement on OVL. The position statement should indicate the following:
a- Will you support OVL (support is not just mere word, but clear involvement to improve or correct the current OVL).
b- If OVL is not adequate, what modification or additional capability required to help change your position.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
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