Subject: RE: Thursday's Meeting at Mentor
From: Vassilios.Gerousis@Infineon.Com
Date: Thu Mar 14 2002 - 07:39:39 PST
Here is the Agenda:
The plan is to have HDL+ Committee (Verilog++ and Assertion Committee) as a full day 9:00 AM until 4:00 PM
I cannot say when we will start the assertion, but the target is to shoot for 2:00 PM
The Agenda topic is number 6.
1- Introduction And Agenda Discussions Starts at 9:00 AM
2- Synchronization And Milestones (SystemVerilog Release).
3- Issue List Tracking.
4- Draft 4 Review:
- Editors Comments.
- Reviewer Comments.
5- Assertion Presentation by Co-design.
6- Assertion Goals Revisited:
a- High Level Assertion:
- OVL.
- Position Statement from members.
- Use model with SystemVerilog
b- Verilog Assertions Primitive (DAS).
- Conduct of activities.
- Conformance to requirement document.
c- Guidance for
-----Original Message-----
From: Harry Foster [mailto:harry@verplex.com]
Sent: Thursday, March 14, 2002 6:37 AM
To: Vassilios. Gerousis
Cc: assertion@eda.org
Subject: Thursday's Meeting at Mentor
Hi Vassilios,
I forgot to ask you today when we met. What is the
schedule for tomorrow's meeting? I plan to be there
all day. However, there are a number of assertion
committee members that would like to attend--but really
are only interested in attending the assertions portion
of the meeting.
Best regards,
-Harry
---------------------------------------------------------
Harry Foster Tel XXX-XXX-XXXX
Chief Architect Cell XXX-XXX-XXXX
Verplex Systems, Inc. mailto:harry@verplex.com
300 Montague Expwy, Suite 100 www.verplex.com
Milpitas, CA 95035 www.verifiableRTL.com
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