RE: Time to Start Up Again!


Subject: RE: Time to Start Up Again!
From: Harry Foster (harry@verplex.com)
Date: Fri Mar 01 2002 - 09:16:01 PST


Hi Vassilios,

The DAS will provide the ability to express a broader
class of assertions than the OVL.

Concerning the OVL--my plan is to re-code a Verilog
version of OVL using the new DAS construct. This
demonstrates my claim of one of the benefits of the OVL:
Existing designs can migrate seamlessly to the new DAS
construct, by encapsulating the changes within the OVL library.
Furthermore, the OVL permits seamless evaluation of
existing (and future) tools containing their own
proprietary pragma assertion mechanisms.

I will take the responsibility of recoding the Verilog
version of the OVL using the new DAS construct.

Obviously, the VHDL version of the OVL will never
contain the DAS. Many designs today consist of both
VHDL and Verilog. The OVL provides a consistent
assertion mechanism between the two languages.

Best regards,

-Harry

> -----Original Message-----
> From: owner-assertion@eda.org [mailto:owner-assertion@eda.org]On Behalf
> Of Vassilios.Gerousis@Infineon.Com
> Sent: Friday, March 01, 2002 10:45 AM
> To: fitz@co-design.com; assertion@eda.org
> Cc: davek@co-design.com; simond@co-design.com
> Subject: RE: Time to Start Up Again!
>
>
> Hello Tom,
> Please work with David Lacey, the current chairman of
> assertion committee, to arrange meeting with the assertion
> committee. We will have a detailed discussion on March 14 at
> Mentor Graphics as a face to face meeting with the Verilog++
> committee. During this we will invite all assertion members to
> attend this meeting to help us synchronize on the final delivery
> for May 1. We will also review in detail the DAS proposal.
>
> Two things that I see missing today:
>
> 1- How does DAS fit with other constructs defined in
> SystemVerilog? Can it be used anywhere?
>
> 2- OVL and DAS synchronization: How does DAS implement the 35
> functions defined in OVL?
>
> Vassilios
>
> -----Original Message-----
> From: Tom Fitzpatrick [mailto:fitz@co-design.com]
> Sent: Friday, March 01, 2002 5:25 PM
> To: assertion@eda.org
> Cc: Dave Kelf; Simon Davidmann
> Subject: Time to Start Up Again!
>
>
> Hi All,
>
> The SUPERLOG Design Assertion Subset donation is finally
> complete. As such,
> I'd like to schedule a series of committee meetings so that we can make up
> for lost time.
>
> I know that our course previously had been to have meetings on Thursdays,
> but that won't work for the next two weeks. Next week, I'd like to propose
> we meet at 9:00am PST/12pm EST on Friday, 3/8. This is to accomodate Peter
> Flake's DATE travel schedule. The agenda for this meeting is to go through
> the donated spec (to be distributed early next week) and make sure that
> everyone is up to speed on what's in it and why. Peter is
> essential to this
> discussion.
>
> I'd like to have the next meeting after that in person in San
> Jose the week
> of HDLCon. Wednesday that week works best for us. Can someone can
> provide a
> meeting room at their local office? This meeting will be to build
> a list of
> issues that everyone has from the initial review. I'd like to
> prioritize the
> sections of the spec, and put together a timeline to get all
> issues resolved
> in time to meet the SystemVerilog schedule.
>
> At Friday's meeting, we can also discuss future meetings, but I'd like to
> aim for weekly meetings at least through March.
>
> Thanks for your patience, cooperation and effort.
> -Tom
>
>
> +----------------------------+------------------------------------------+
> | Tom Fitzpatrick | Tel: 1 978 448 8797 |
> | Technical Product Manager | Mobile: 1 978 337 7641 |
> | Co-Design Automation, Inc. | email: fitz@co-design.com |
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