RE: Time to Start Up Again!


Subject: RE: Time to Start Up Again!
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Mar 01 2002 - 08:44:52 PST


Hello Tom,
        Please work with David Lacey, the current chairman of assertion committee, to arrange meeting with the assertion committee. We will have a detailed discussion on March 14 at Mentor Graphics as a face to face meeting with the Verilog++ committee. During this we will invite all assertion members to attend this meeting to help us synchronize on the final delivery for May 1. We will also review in detail the DAS proposal.

        Two things that I see missing today:

1- How does DAS fit with other constructs defined in SystemVerilog? Can it be used anywhere?

2- OVL and DAS synchronization: How does DAS implement the 35 functions defined in OVL?

Vassilios

-----Original Message-----
From: Tom Fitzpatrick [mailto:fitz@co-design.com]
Sent: Friday, March 01, 2002 5:25 PM
To: assertion@eda.org
Cc: Dave Kelf; Simon Davidmann
Subject: Time to Start Up Again!

Hi All,

The SUPERLOG Design Assertion Subset donation is finally complete. As such,
I'd like to schedule a series of committee meetings so that we can make up
for lost time.

I know that our course previously had been to have meetings on Thursdays,
but that won't work for the next two weeks. Next week, I'd like to propose
we meet at 9:00am PST/12pm EST on Friday, 3/8. This is to accomodate Peter
Flake's DATE travel schedule. The agenda for this meeting is to go through
the donated spec (to be distributed early next week) and make sure that
everyone is up to speed on what's in it and why. Peter is essential to this
discussion.

I'd like to have the next meeting after that in person in San Jose the week
of HDLCon. Wednesday that week works best for us. Can someone can provide a
meeting room at their local office? This meeting will be to build a list of
issues that everyone has from the initial review. I'd like to prioritize the
sections of the spec, and put together a timeline to get all issues resolved
in time to meet the SystemVerilog schedule.

At Friday's meeting, we can also discuss future meetings, but I'd like to
aim for weekly meetings at least through March.

Thanks for your patience, cooperation and effort.
-Tom

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