Subject: Minutes for the Assertion Committee Meeting 2/12/2002
From: Harry Foster (harry@verplex.com)
Date: Tue Feb 12 2002 - 16:48:26 PST
Minutes for the Assertion Committee Meeting 2/12/2002.
Meeting Attendees:
Harry Foster (Verplex)
Michal Siwinski (Verplex)
Henry Cox (Co-design)
Sean Smith (Cisco)
David Lacey (Hewlett-Packard)
Joe Richard (SGI)
In today's meeting, we discussed the IEEE standardization
effort for the OVL.
In addition, we discussed the VHDL OVL donation
to Accellera. The assertion committee decided to form
a subcommittee to maintain and oversee the VHDL implementation.
Harry will solicite sub-committee participation from
current reviewers of the VHDL OVL.
Sean Smith will propose an enhanced OVL implementation
for severity level controllability and reporting.
The committee will review his implementation and roll
the enhancements into a future release of the library.
Harry proposed 3 new assertions. The main discussion
was on the new 'assert_set', used to validate
the value of a variable (like a bus tag) is
contained within a legal set -- or as an option,
the variable (or expression) is not contained within
a set. The simple mechanism proposed can handle an
arbitrary large set. Harry will finish coding the
implementation and pass it on to the committee for
review.
In addition, Harry proposed a new idea of adding
an optional output port to the OVL assertions. This
would enable the user to build up more complex assertions
and constraint models --by linking assertions together
(output chaining). This provides the expressiveness,
discussed in the System Verilog assert construct
requirements document, of regular expression.
Best regards,
-Harry
---------------------------------------------------------
Harry Foster Tel XXX-XXX-XXXX
Chief Architect Cell XXX-XXX-XXXX
Verplex Systems, Inc. mailto:harry@verplex.com
300 Montague Expwy, Suite 100 www.verplex.com
Milpitas, CA 95035 www.verifiableRTL.com
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